From 7a68d9ed0d7182f01da982bf48a759b4f70504d8 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Duje=20Mihanovi=C4=87?= Date: Sun, 4 Sep 2022 17:20:43 +0200 Subject: [PATCH] DONOTMERGE: Enable AArch64 system timer properly With this, an initramfs can be reached. Long-term, this will be moved someplace such as U-Boot. --- drivers/clk/mmp/clk-pxa1908-apbc.c | 31 +++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mmp/clk-pxa1908-apbc.c b/drivers/clk/mmp/clk-pxa1908-apbc.c index a418b9f895c1..6f71c46c2725 100644 --- a/drivers/clk/mmp/clk-pxa1908-apbc.c +++ b/drivers/clk/mmp/clk-pxa1908-apbc.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only +#include #include #include #include @@ -30,6 +31,8 @@ #define APBC_NR_CLKS 19 +#define APBC_COUNTER_CLK_SEL 0x64 + struct pxa1908_clk_unit { struct mmp_clk_unit unit; void __iomem *base; @@ -108,6 +111,21 @@ static int pxa1908_apbc_probe(struct platform_device *pdev) pxa1908_apb_periph_clk_init(pxa_unit); + /* Assign a 26MHz clock to the ARM architected timer. */ + int tmp = readl(pxa_unit->base + APBC_COUNTER_CLK_SEL); + if ((tmp >> 16) == 0x319) { + writel(tmp | 1, pxa_unit->base + APBC_COUNTER_CLK_SEL); + } + + /* Enable the ARM architected timer. */ + void __iomem *cnt_base = ioremap(0xd4101000, 0x1000); + if (!cnt_base) + pr_err("failed to map cnt register\n"); + else { + writel(BIT(0) | BIT(1), cnt_base); + iounmap(cnt_base); + } + return 0; } @@ -124,7 +142,18 @@ static struct platform_driver pxa1908_apbc_driver = { .of_match_table = pxa1908_apbc_match_table } }; -module_platform_driver(pxa1908_apbc_driver); + +static int __init pxa1908_apbc_init(void) +{ + return platform_driver_register(&pxa1908_apbc_driver); +} +core_initcall(pxa1908_apbc_init); + +static void __exit pxa1908_apbc_exit(void) +{ + platform_driver_unregister(&pxa1908_apbc_driver); +} +module_exit(pxa1908_apbc_exit); MODULE_AUTHOR("Duje Mihanović "); MODULE_DESCRIPTION("Marvell PXA1908 APBC Clock Driver"); -- 2.39.5