From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun, 24 Jul 2011 17:20:54 +0000 (-0700)
Subject: Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
X-Git-Tag: v6.6-pxa1908~29942
X-Git-Url: https://git.dujemihanovic.xyz/?a=commitdiff_plain;h=b6844e8f64920cdee620157252169ba63afb0c89;p=linux.git

Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (237 commits)
  ARM: 7004/1: fix traps.h compile warnings
  ARM: 6998/2: kernel: use proper memory barriers for bitops
  ARM: 6997/1: ep93xx: increase NR_BANKS to 16 for support of 128MB RAM
  ARM: Fix build errors caused by adding generic macros
  ARM: CPU hotplug: ensure we migrate all IRQs off a downed CPU
  ARM: CPU hotplug: pass in proper affinity mask on IRQ migration
  ARM: GIC: avoid routing interrupts to offline CPUs
  ARM: CPU hotplug: fix abuse of irqdesc->node
  ARM: 6981/2: mmci: adjust calculation of f_min
  ARM: 7000/1: LPAE: Use long long printk format for displaying the pud
  ARM: 6999/1: head, zImage: Always Enter the kernel in ARM state
  ARM: btc: avoid invalidating the branch target cache on kernel TLB maintanence
  ARM: ARM_DMA_ZONE_SIZE is no more
  ARM: mach-shark: move ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size
  ARM: mach-sa1100: move ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size
  ARM: mach-realview: move from ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size
  ARM: mach-pxa: move from ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size
  ARM: mach-ixp4xx: move from ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size
  ARM: mach-h720x: move from ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size
  ARM: mach-davinci: move from ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size
  ...
---

b6844e8f64920cdee620157252169ba63afb0c89
diff --cc arch/arm/kernel/perf_event_v7.c
index e20ca9cafef5,963317896c80..4c851834f68e
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@@ -385,22 -409,244 +423,258 @@@ static const unsigned armv7_a9_perf_cac
  			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
  		},
  	},
 +	[C(NODE)] = {
 +		[C(OP_READ)] = {
 +			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
 +			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
 +		},
 +		[C(OP_WRITE)] = {
 +			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
 +			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
 +		},
 +		[C(OP_PREFETCH)] = {
 +			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
 +			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
 +		},
 +	},
  };
  
+ /*
+  * Cortex-A5 HW events mapping
+  */
+ static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
+ 	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,
+ 	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV7_PERFCTR_INSTR_EXECUTED,
+ 	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+ 	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,
+ 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+ 	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ 	[PERF_COUNT_HW_BUS_CYCLES]	    = HW_OP_UNSUPPORTED,
+ };
+ 
+ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+ 					[PERF_COUNT_HW_CACHE_OP_MAX]
+ 					[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+ 	[C(L1D)] = {
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]
+ 					= ARMV7_PERFCTR_DCACHE_ACCESS,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_DCACHE_REFILL,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]
+ 					= ARMV7_PERFCTR_DCACHE_ACCESS,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_DCACHE_REFILL,
+ 		},
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]
+ 					= ARMV7_PERFCTR_PREFETCH_LINEFILL,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
+ 		},
+ 	},
+ 	[C(L1I)] = {
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+ 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+ 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
+ 		},
+ 		/*
+ 		 * The prefetch counters don't differentiate between the I
+ 		 * side and the D side.
+ 		 */
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]
+ 					= ARMV7_PERFCTR_PREFETCH_LINEFILL,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
+ 		},
+ 	},
+ 	[C(LL)] = {
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 	},
+ 	[C(DTLB)] = {
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DTLB_REFILL,
+ 		},
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 	},
+ 	[C(ITLB)] = {
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
+ 		},
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 	},
+ 	[C(BPU)] = {
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ 		},
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 	},
+ };
+ 
+ /*
+  * Cortex-A15 HW events mapping
+  */
+ static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
+ 	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,
+ 	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV7_PERFCTR_INSTR_EXECUTED,
+ 	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+ 	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,
+ 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_SPEC_PC_WRITE,
+ 	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ 	[PERF_COUNT_HW_BUS_CYCLES]	    = ARMV7_PERFCTR_BUS_CYCLES,
+ };
+ 
+ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+ 					[PERF_COUNT_HW_CACHE_OP_MAX]
+ 					[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+ 	[C(L1D)] = {
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]
+ 					= ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_L1_DCACHE_READ_REFILL,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]
+ 					= ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL,
+ 		},
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 	},
+ 	[C(L1I)] = {
+ 		/*
+ 		 * Not all performance counters differentiate between read
+ 		 * and write accesses/misses so we're not always strictly
+ 		 * correct, but it's the best we can do. Writes and reads get
+ 		 * combined in these cases.
+ 		 */
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+ 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+ 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,
+ 		},
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 	},
+ 	[C(LL)] = {
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]
+ 					= ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_L2_DCACHE_READ_REFILL,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]
+ 					= ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL,
+ 		},
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 	},
+ 	[C(DTLB)] = {
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_L1_DTLB_READ_REFILL,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL,
+ 		},
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 	},
+ 	[C(ITLB)] = {
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,
+ 		},
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 	},
+ 	[C(BPU)] = {
+ 		[C(OP_READ)] = {
+ 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ 		},
+ 		[C(OP_WRITE)] = {
+ 			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,
+ 			[C(RESULT_MISS)]
+ 					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+ 		},
+ 		[C(OP_PREFETCH)] = {
+ 			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+ 			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+ 		},
+ 	},
+ };
+ 
  /*
   * Perf Events counters
   */