From: Ben Widawsky Date: Tue, 9 Apr 2013 01:43:47 +0000 (-0700) Subject: drm/i915: generalize pte vs. register BAR allocation X-Git-Tag: v6.6-pxa1908~25584^2~40^2~41 X-Git-Url: https://git.dujemihanovic.xyz/?a=commitdiff_plain;h=a93e41618ecf69a2ced005a13377d7903da4dd62;p=linux.git drm/i915: generalize pte vs. register BAR allocation All gen6+ parts so far have 1 BAR which holds both the register space and the GTT PTEs. Up until now, that was a 4MB BAR with half allocated to each. I have a strong hunch (wink, nod, wink) that future gens will also keep a similar 50-50 split though the sizes may change. To help this along change the code to obey the rule of half the total size instead of a hard-coded 2MB. Signed-off-by: Ben Widawsky Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 24a23b31b55f..215d72ce3f67 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -738,8 +738,10 @@ static int gen6_gmch_probe(struct drm_device *dev, *gtt_total = (gtt_size / sizeof(gtt_pte_t)) << PAGE_SHIFT; - /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */ - gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20); + /* For Modern GENs the PTEs and register space are split in the BAR */ + gtt_bus_addr = pci_resource_start(dev->pdev, 0) + + (pci_resource_len(dev->pdev, 0) / 2); + dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); if (!dev_priv->gtt.gsm) { DRM_ERROR("Failed to map the gtt page table\n");