From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Thu, 4 Apr 2013 12:13:41 +0000 (+0300)
Subject: drm/i915: Set GAC_ECO_BITS register on Gen7+
X-Git-Tag: v6.6-pxa1908~25584^2~40^2~27
X-Git-Url: https://git.dujemihanovic.xyz/?a=commitdiff_plain;h=a65c2fcd00518b7339d72e08e6b2b4261fbcc22a;p=linux.git

drm/i915: Set GAC_ECO_BITS register on Gen7+

According to BSpec GAC_ECO_BITS register exists on Gen7 platforms as
well. Configure it accordingly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a336c4d609a2..fae638072d7d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -117,6 +117,11 @@ static int gen6_ppgtt_enable(struct drm_device *dev)
 				       ECOCHK_PPGTT_CACHE64B);
 		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 	} else if (INTEL_INFO(dev)->gen >= 7) {
+		uint32_t ecobits;
+
+		ecobits = I915_READ(GAC_ECO_BITS);
+		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
+
 		I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 		/* GFX_MODE is per-ring on gen7+ */
 	}