From: Dave Airlie <airlied@redhat.com>
Date: Thu, 27 Feb 2014 04:39:30 +0000 (+1000)
Subject: Merge branch 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux into... 
X-Git-Tag: v6.6-pxa1908~23483^2~60
X-Git-Url: https://git.dujemihanovic.xyz/?a=commitdiff_plain;h=4d538b79197901fecc42e746d515d07fd1089b62;p=linux.git

Merge branch 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-next

So this is the initial pull request for radeon drm-next 3.15. Highlights:
- VCE bringup including DPM support
- Few cleanups for the ring handling code

* 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux:
  drm/radeon: cleanup false positive lockup handling
  drm/radeon: drop radeon_ring_force_activity
  drm/radeon: drop drivers copy of the rptr
  drm/radeon/cik: enable/disable vce cg when encoding v2
  drm/radeon: add support for vce 2.0 clock gating
  drm/radeon/dpm: properly enable/disable vce when vce pg is enabled
  drm/radeon/dpm: enable dynamic vce state switching v2
  drm/radeon: add vce dpm support for KV/KB
  drm/radeon: enable vce dpm on CI
  drm/radeon: add vce dpm support for CI
  drm/radeon: fill in set_vce_clocks for CIK asics
  drm/radeon/dpm: fetch vce states from the vbios
  drm/radeon/dpm: fill in some initial vce infrastructure
  drm/radeon/dpm: move platform caps fetching to a separate function
  drm/radeon: add callback for setting vce clocks
  drm/radeon: add VCE version parsing and checking
  drm/radeon: add VCE ring query
  drm/radeon: initial VCE support v4
  drm/radeon: fix CP semaphores on CIK
---

4d538b79197901fecc42e746d515d07fd1089b62
diff --cc drivers/gpu/drm/radeon/radeon.h
index 024db37b1832,a415f8e9d972..4581df193932
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@@ -133,11 -130,18 +130,21 @@@ extern int radeon_hard_reset
  #define CAYMAN_RING_TYPE_DMA1_INDEX		4
  
  /* R600+ */
- #define R600_RING_TYPE_UVD_INDEX	5
+ #define R600_RING_TYPE_UVD_INDEX		5
+ 
+ /* TN+ */
+ #define TN_RING_TYPE_VCE1_INDEX			6
+ #define TN_RING_TYPE_VCE2_INDEX			7
+ 
+ /* max number of rings */
+ #define RADEON_NUM_RINGS			8
+ 
+ /* number of hw syncs before falling back on blocking */
+ #define RADEON_NUM_SYNCS			4
  
 +/* number of hw syncs before falling back on blocking */
 +#define RADEON_NUM_SYNCS			4
 +
  /* hardcode those limit for now */
  #define RADEON_VA_IB_OFFSET			(1 << 20)
  #define RADEON_VA_RESERVED_SIZE			(8 << 20)