From: Palmer Dabbelt Date: Thu, 22 Jun 2023 21:23:56 +0000 (-0700) Subject: Merge patch series "dt-bindings: riscv: cpus: switch to unevaluatedProperties: false" X-Git-Tag: v6.6-pxa1908~872^2 X-Git-Url: https://git.dujemihanovic.xyz/?a=commitdiff_plain;h=488833ccdcac118da16701f4ee0673b20ba47fe3;p=linux.git Merge patch series "dt-bindings: riscv: cpus: switch to unevaluatedProperties: false" Conor Dooley says: From: Conor Dooley Do the various bits needed to drop the additionalProperties: true that we currently have in riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes. * b4-shazam-merge: dt-bindings: riscv: cpus: switch to unevaluatedProperties: false dt-bindings: riscv: cpus: add a ref the common cpu schema Link: https://lore.kernel.org/r/20230615-creamer-emu-ade0fa0bdb68@spud Signed-off-by: Palmer Dabbelt --- 488833ccdcac118da16701f4ee0673b20ba47fe3 diff --cc Documentation/devicetree/bindings/riscv/cpus.yaml index c2ed979c9428,144da86718c1..67bd239ead0b --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@@ -94,10 -97,13 +97,13 @@@ properties While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all - lowercase to simplify parsing. - $ref: "/schemas/types.yaml#/definitions/string" + lowercase. + $ref: /schemas/types.yaml#/definitions/string pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + # RISC-V has multiple properties for cache op block sizes as the sizes + # differ between individual CBO extensions + cache-op-block-size: false # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false