drm/amd/display: Add missing mcache registers

Add missing register programming for mcache in DCN401.

Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit a00a177055cced5cd2bb057a1ace9a95a286bc49)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
index 26efeada4f41fd7649fa7ad0311ec3ef9c5b6132..bb46f30d11d0a1ef5f38d8fba3c9d30cb46dfbc8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
@@ -138,7 +138,9 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
        SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id),                                   \
        SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id),                                   \
        SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id),                                 \
-       HUBP_3DLUT_FL_REG_LIST_DCN401(id)
+       HUBP_3DLUT_FL_REG_LIST_DCN401(id),                                       \
+       SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id),              \
+       SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id)
 
 /* ABM */
 #define ABM_DCN401_REG_LIST_RI(id)                                            \