drm/amd/display: Add visual confirm color support for MCLK switch

[Why && How]
We would like to have visual confirm color support for MCLK switch.
	1. Set visual confirm color to yellow: Vblank MCLK switch.
	2. Set visual confirm color to cyan: FPO + Vblank MCLK
	switch.
	3. Set visual confirm color to pink: Vactive MCLK switch.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c26dfdd48dd93806a5dccb86bcd2511d3daa13bf..2c639cd346d78cffc0885a9b6ec19e4e59177727 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1119,6 +1119,33 @@ static void phantom_pipe_blank(
                hws->funcs.wait_for_blank_complete(opp);
 }
 
+static void dc_update_viusal_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
+{
+       if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
+               memset(&pipe_ctx->visual_confirm_color, 0, sizeof(struct tg_color));
+
+               if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
+                       get_hdr_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
+               else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
+                       get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
+               else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
+                       get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
+               else {
+                       if (dc->ctx->dce_version < DCN_VERSION_2_0)
+                               color_space_to_black_color(
+                                       dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));
+               }
+               if (dc->ctx->dce_version >= DCN_VERSION_2_0) {
+                       if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
+                               get_mpctree_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
+                       else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
+                               get_subvp_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
+                       else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)
+                               get_mclk_switch_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
+               }
+       }
+}
+
 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 {
        int i, j;
@@ -1189,6 +1216,9 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
                        dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
                        disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 
+                       if (pipe->stream && pipe->plane_state)
+                               dc_update_viusal_confirm_color(dc, context, pipe);
+
                        if (dc->hwss.apply_ctx_for_surface) {
                                apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
                                dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
@@ -3456,6 +3486,14 @@ static void commit_planes_for_stream(struct dc *dc,
                }
        }
 
+       if (dc->debug.visual_confirm)
+               for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                       struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+                       if (pipe->stream && pipe->plane_state)
+                               dc_update_viusal_confirm_color(dc, context, pipe);
+               }
+
        if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
                struct pipe_ctx *mpcc_pipe;
                struct pipe_ctx *odm_pipe;
@@ -3539,15 +3577,14 @@ static void commit_planes_for_stream(struct dc *dc,
                for (j = 0; j < dc->res_pool->pipe_count; j++) {
                        struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
 
-                       if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP &&
+                       if ((dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP ||
+                               dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH) &&
                                pipe_ctx->stream && pipe_ctx->plane_state) {
-                               /* Only update visual confirm for SUBVP here.
+                               /* Only update visual confirm for SUBVP and Mclk switching here.
                                 * The bar appears on all pipes, so we need to update the bar on all displays,
                                 * so the information doesn't get stale.
                                 */
-                               struct mpcc_blnd_cfg blnd_cfg = { 0 };
-
-                               dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color,
+                               dc->hwss.update_visual_confirm_color(dc, pipe_ctx,
                                                pipe_ctx->plane_res.hubp->inst);
                        }
                }

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 2acbf692193f7728f0ef17ad78022002dffb9791..8a98b8dd008ef34f66efca71795a63fe30536c98 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -421,6 +421,7 @@ void get_hdr_visual_confirm_color(
 
 void get_subvp_visual_confirm_color(
                struct dc *dc,
+               struct dc_state *context,
                struct pipe_ctx *pipe_ctx,
                struct tg_color *color)
 {
@@ -428,15 +429,17 @@ void get_subvp_visual_confirm_color(
        bool enable_subvp = false;
        int i;
 
-       if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx)
+       if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context)
                return;
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
-               struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+               struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 
                if (pipe->stream && pipe->stream->mall_stream_config.paired_stream &&
                    pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
                        /* SubVP enable - red */
+                       color->color_g_y = 0;
+                       color->color_b_cb = 0;
                        color->color_r_cr = color_value;
                        enable_subvp = true;
 
@@ -448,12 +451,51 @@ void get_subvp_visual_confirm_color(
 
        if (enable_subvp && pipe_ctx->stream->mall_stream_config.type == SUBVP_NONE) {
                color->color_r_cr = 0;
-               if (pipe_ctx->stream->ignore_msa_timing_param == 1)
+               if (pipe_ctx->stream->allow_freesync == 1) {
                        /* SubVP enable and DRR on - green */
+                       color->color_b_cb = 0;
                        color->color_g_y = color_value;
-               else
+               } else {
                        /* SubVP enable and No DRR - blue */
+                       color->color_g_y = 0;
+                       color->color_b_cb = color_value;
+               }
+       }
+}
+
+void get_mclk_switch_visual_confirm_color(
+               struct dc *dc,
+               struct dc_state *context,
+               struct pipe_ctx *pipe_ctx,
+               struct tg_color *color)
+{
+       uint32_t color_value = MAX_TG_COLOR_VALUE;
+       struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+
+       if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba || !context)
+               return;
+
+       if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] !=
+                       dm_dram_clock_change_unsupported) {
+               /* MCLK switching is supported */
+               if (!pipe_ctx->has_vactive_margin) {
+                       /* In Vblank - yellow */
+                       color->color_r_cr = color_value;
+                       color->color_g_y = color_value;
+
+                       if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
+                               /* FPO + Vblank - cyan */
+                               color->color_r_cr = 0;
+                               color->color_g_y  = color_value;
+                               color->color_b_cb = color_value;
+                       }
+               } else {
+                       /* In Vactive - pink */
+                       color->color_r_cr = color_value;
                        color->color_b_cb = color_value;
+               }
+               /* SubVP */
+               get_subvp_visual_confirm_color(dc, context, pipe_ctx, color);
        }
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 1ebb8d3573f48884989c62978c80702a3a882cfc..8be2e6d6d88848674b547ff13ae55e2c1e2eaaeb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -426,6 +426,7 @@ enum visual_confirm {
        VISUAL_CONFIRM_FAMS = 7,
        VISUAL_CONFIRM_SWIZZLE = 9,
        VISUAL_CONFIRM_SUBVP = 14,
+       VISUAL_CONFIRM_MCLK_SWITCH = 16,
 };
 
 enum dc_psr_power_opts {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index a7ad1d7bc43e523bad741d07bed4ecb2bc8447d6..905246a2ece45974df9857ac7f592eaf925788c5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2602,23 +2602,15 @@ static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state
                dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
 }
 
-void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
+void dcn10_update_visual_confirm_color(struct dc *dc,
+               struct pipe_ctx *pipe_ctx,
+               int mpcc_id)
 {
        struct mpc *mpc = dc->res_pool->mpc;
 
-       if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
-               get_hdr_visual_confirm_color(pipe_ctx, color);
-       else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
-               get_surface_visual_confirm_color(pipe_ctx, color);
-       else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
-               get_surface_tile_visual_confirm_color(pipe_ctx, color);
-       else
-               color_space_to_black_color(
-                               dc, pipe_ctx->stream->output_color_space, color);
-
        if (mpc->funcs->set_bg_color) {
-               memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color));
-               mpc->funcs->set_bg_color(mpc, color, mpcc_id);
+               memcpy(&pipe_ctx->plane_state->visual_confirm_color, &(pipe_ctx->visual_confirm_color), sizeof(struct tg_color));
+               mpc->funcs->set_bg_color(mpc, &(pipe_ctx->visual_confirm_color), mpcc_id);
        }
 }
 
@@ -2671,7 +2663,7 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
        /* If there is no full update, don't need to touch MPC tree*/
        if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
                mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
-               dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
+               dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
                return;
        }
 
@@ -2693,7 +2685,7 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
                        NULL,
                        hubp->inst,
                        mpcc_id);
-       dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
+       dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
 
        ASSERT(new_mpcc != NULL);
        hubp->opp_id = pipe_ctx->stream_res.opp->inst;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 0ef7bf7ddb75e918472f92577837de7907bdebfb..ef6d56da417cdffb6b15de4529972d8ef3795bc4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -202,7 +202,6 @@ void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);
 void dcn10_update_visual_confirm_color(
                struct dc *dc,
                struct pipe_ctx *pipe_ctx,
-               struct tg_color *color,
                int mpcc_id);
 
 #endif /* __DC_HWSS_DCN10_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index f49c1c0d627478db9a104a5aaf837c19e858ab9f..b3e187b1347d873fffc4935c08fb32ba000401cd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2580,28 +2580,6 @@ void dcn20_reset_hw_ctx_wrap(
        }
 }
 
-void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
-{
-       struct mpc *mpc = dc->res_pool->mpc;
-
-       // input to MPCC is always RGB, by default leave black_color at 0
-       if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
-               get_hdr_visual_confirm_color(pipe_ctx, color);
-       else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
-               get_surface_visual_confirm_color(pipe_ctx, color);
-       else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
-               get_mpctree_visual_confirm_color(pipe_ctx, color);
-       else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
-               get_surface_tile_visual_confirm_color(pipe_ctx, color);
-       else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
-               get_subvp_visual_confirm_color(dc, pipe_ctx, color);
-
-       if (mpc->funcs->set_bg_color) {
-               memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color));
-               mpc->funcs->set_bg_color(mpc, color, mpcc_id);
-       }
-}
-
 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
        struct hubp *hubp = pipe_ctx->plane_res.hubp;
@@ -2657,7 +2635,7 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
        if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
                !pipe_ctx->update_flags.bits.mpcc) {
                mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
-               dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
+               dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
                return;
        }
 
@@ -2679,7 +2657,7 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
                        NULL,
                        hubp->inst,
                        mpcc_id);
-       dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
+       dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
 
        ASSERT(new_mpcc != NULL);
        hubp->opp_id = pipe_ctx->stream_res.opp->inst;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index 33a36c02b2f8f6b09032e738de53d2cbc5ae180a..01901b08644c584b539d6e9718b1bf8ec72f47f6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -150,10 +150,5 @@ void dcn20_set_disp_pattern_generator(const struct dc *dc,
                const struct tg_color *solid_color,
                int width, int height, int offset);
 
-void dcn20_update_visual_confirm_color(struct dc *dc,
-               struct pipe_ctx *pipe_ctx,
-               struct tg_color *color,
-               int mpcc_id);
-
 #endif /* __DC_HWSS_DCN20_H__ */
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index 7c5817c426faa78c55da31ac1eacf83c315fb737..4192c522e59aa6f900307a30627548fe1bb4de75 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -102,7 +102,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
        .disable_link_output = dce110_disable_link_output,
        .set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
        .get_dcc_en_bits = dcn10_get_dcc_en_bits,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color
+       .update_visual_confirm_color = dcn10_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn20_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
index 1aeb04fbd89d322fa0ba48fe67788f2709c0d8b3..75472d53ff52f33c6365918a49cdba76e1c1b662 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
@@ -496,7 +496,7 @@ void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 
        /* If there is no full update, don't need to touch MPC tree*/
        if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
-               dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
+               dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
                mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
                return;
        }
@@ -521,7 +521,7 @@ void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
                                        dc->res_pool->mpc, mpcc_id);
 
        /* Call MPC to insert new plane */
-       dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
+       dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
        new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
                        mpc_tree_params,
                        &blnd_cfg,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c
index 9c16633e473a0ff87de4589e60a7e88adbd7aa2f..92dd4cddbab8aa143ed8ad91e20f2dc6fe720e2d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c
@@ -91,7 +91,7 @@ static const struct hw_sequencer_funcs dcn201_funcs = {
        .enable_dp_link_output = dce110_enable_dp_link_output,
        .disable_link_output = dce110_disable_link_output,
        .set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
+       .update_visual_confirm_color = dcn10_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn201_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index fe1a8e2e08ef1bf689ce33c3f99a810c68802a02..8b58ce1db03524d075acae4b153ab32088cb8632 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -106,7 +106,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
        .is_abm_supported = dcn21_is_abm_supported,
        .set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
        .get_dcc_en_bits = dcn10_get_dcc_en_bits,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
+       .update_visual_confirm_color = dcn10_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn21_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index 3216d10c58ba71d31bfd992e7f28e30769a5194b..18e94d8ae54fcd688f12c6cbcb770611043e9a86 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -106,7 +106,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
        .disable_link_output = dce110_disable_link_output,
        .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
        .get_dcc_en_bits = dcn10_get_dcc_en_bits,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
+       .update_visual_confirm_color = dcn10_update_visual_confirm_color,
        .is_abm_supported = dcn21_is_abm_supported
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
index 6192851c59ed8950653ba4668177417eb2cf1a3d..257df8660b4cafef2a64231487729bbd2d4b3486 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
@@ -107,7 +107,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = {
        .get_dcc_en_bits = dcn10_get_dcc_en_bits,
        .optimize_pwr_state = dcn21_optimize_pwr_state,
        .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
+       .update_visual_confirm_color = dcn10_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn301_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
index 8598ea233ef3ea465f6f69c62b6179d422095710..ba9e7dee6e5e5add2a91092c164cce881c9799f5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
@@ -110,7 +110,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
        .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
        .optimize_pwr_state = dcn21_optimize_pwr_state,
        .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
+       .update_visual_confirm_color = dcn10_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn31_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
index ed8a1b94c00681ada8f2308571174f14f90b4555..7a28c7bb25d20796ef1bf12f86a53e81f0f61d47 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
@@ -112,7 +112,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = {
        .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
        .optimize_pwr_state = dcn21_optimize_pwr_state,
        .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
+       .update_visual_confirm_color = dcn10_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn314_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
index 8085f2acb1a96f0d2906bba1a24ff30f33038205..24a890d879b80165128b8d04983053862a0a88eb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
@@ -109,7 +109,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
        .commit_subvp_config = dcn32_commit_subvp_config,
        .enable_phantom_streams = dcn32_enable_phantom_streams,
        .subvp_pipe_control_lock = dcn32_subvp_pipe_control_lock,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
+       .update_visual_confirm_color = dcn10_update_visual_confirm_color,
        .update_phantom_vp_position = dcn32_update_phantom_vp_position,
        .update_dsc_pg = dcn32_update_dsc_pg,
        .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 8c60b88c7d1abd9cae8e04a045afddf009ad5c48..d8d8fcd5ef1ffb2e27b1da9aca37d25985c10dfc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1324,6 +1324,7 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
        int i, pipe_idx, active_hubp_count = 0;
        bool usr_retraining_support = false;
        bool unbounded_req_enabled = false;
+       struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 
        dc_assert_fp_enabled();
 
@@ -1405,6 +1406,11 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
 
                context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 
+               if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0)
+                       context->res_ctx.pipe_ctx[i].has_vactive_margin = true;
+               else
+                       context->res_ctx.pipe_ctx[i].has_vactive_margin = false;
+
                /* MALL Allocation Sizes */
                /* count from active, top pipes per plane only */
                if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state &&
@@ -2015,6 +2021,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
                                maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
                                dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
                                pstate_en = true;
+                               context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank;
                        } else {
                                /* Restore FCLK latency and re-run validation to go back to original validation
                                 * output if we find that enabling FPO does not give us any benefit (i.e. lower

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 2eb597a24425e9cd666926474501b8071421c125..b4c1cc6dc857f82354007988064f8daf4a93bb2e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -426,6 +426,8 @@ struct pipe_ctx {
        struct dwbc *dwbc;
        struct mcif_wb *mcif_wb;
        union pipe_update_flags update_flags;
+       struct tg_color visual_confirm_color;
+       bool has_vactive_margin;
 };
 
 /* Data used for dynamic link encoder assignment.

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 88ac723d10aa72340fbff0c0903cf28fa1de713e..df160c6a630c0c82e4b2638bd249bb8098f6e920 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -257,7 +257,6 @@ struct hw_sequencer_funcs {
 
        void (*update_visual_confirm_color)(struct dc *dc,
                        struct pipe_ctx *pipe_ctx,
-                       struct tg_color *color,
                        int mpcc_id);
 
        void (*update_phantom_vp_position)(struct dc *dc,
@@ -294,6 +293,7 @@ void get_surface_visual_confirm_color(
 
 void get_subvp_visual_confirm_color(
        struct dc *dc,
+       struct dc_state *context,
        struct pipe_ctx *pipe_ctx,
        struct tg_color *color);
 
@@ -306,4 +306,11 @@ void get_mpctree_visual_confirm_color(
 void get_surface_tile_visual_confirm_color(
                struct pipe_ctx *pipe_ctx,
                struct tg_color *color);
+
+void get_mclk_switch_visual_confirm_color(
+               struct dc *dc,
+               struct dc_state *context,
+               struct pipe_ctx *pipe_ctx,
+               struct tg_color *color);
+
 #endif /* __DC_HW_SEQUENCER_H__ */