drm/xe: Initialize GuC earlier during probe

SR-IOV VF has limited access to MMIO registers. Fortunately, it is able
to access a curated subset that is needed to initialize the driver by
communicating with SR-IOV PF using GuC CT.
Initialize GuC earlier in order to keep the unified probe ordering
between VF and PF modes.

Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240219130530.1406044-4-michal.winiarski@intel.com

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 1cf7561c8b4d924718a695f3901c4c933f0ef5e9..ca85e81fdb44383ffdafdb48a98a843cb1884b71 100644 (file)
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -463,6 +463,12 @@ int xe_device_probe(struct xe_device *xe)
                }
        }
 
+       for_each_gt(gt, xe, id) {
+               err = xe_gt_init_hwconfig(gt);
+               if (err)
+                       return err;
+       }
+
        err = drmm_add_action_or_reset(&xe->drm, xe_driver_flr_fini, xe);
        if (err)
                return err;

diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index fdfb70c7db9f8b1d1e0fe8758a0acde683644cdd..b75f0bf0a9a10f456d35b0ab8a563d524b94e560 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -315,7 +315,6 @@ int xe_gt_init_early(struct xe_gt *gt)
                return err;
 
        xe_gt_topology_init(gt);
-       xe_gt_mcr_init(gt);
 
        err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
        if (err)
@@ -354,8 +353,6 @@ static int gt_fw_domain_init(struct xe_gt *gt)
        if (err)
                goto err_hw_fence_irq;
 
-       xe_pat_init(gt);
-
        if (!xe_gt_is_media_type(gt)) {
                err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt);
                if (err)
@@ -364,19 +361,8 @@ static int gt_fw_domain_init(struct xe_gt *gt)
                        xe_lmtt_init(&gt_to_tile(gt)->sriov.pf.lmtt);
        }
 
-       err = xe_uc_init(&gt->uc);
-       if (err)
-               goto err_force_wake;
-
-       err = xe_uc_init_hwconfig(&gt->uc);
-       if (err)
-               goto err_force_wake;
-
        xe_gt_idle_sysfs_init(&gt->gtidle);
 
-       /* XXX: Fake that we pull the engine mask from hwconfig blob */
-       gt->info.engine_mask = gt->info.__engine_mask;
-
        /* Enable per hw engine IRQs */
        xe_irq_enable_hwe(gt);
 
@@ -444,10 +430,6 @@ static int all_fw_domain_init(struct xe_gt *gt)
        if (err)
                goto err_force_wake;
 
-       err = xe_uc_init_post_hwconfig(&gt->uc);
-       if (err)
-               goto err_force_wake;
-
        if (!xe_gt_is_media_type(gt)) {
                /*
                 * USM has its only SA pool to non-block behind user operations
@@ -474,6 +456,10 @@ static int all_fw_domain_init(struct xe_gt *gt)
                }
        }
 
+       err = xe_uc_init_post_hwconfig(&gt->uc);
+       if (err)
+               goto err_force_wake;
+
        err = xe_uc_init_hw(&gt->uc);
        if (err)
                goto err_force_wake;
@@ -503,6 +489,41 @@ err_hw_fence_irq:
        return err;
 }
 
+/*
+ * Initialize enough GT to be able to load GuC in order to obtain hwconfig and
+ * enable CTB communication.
+ */
+int xe_gt_init_hwconfig(struct xe_gt *gt)
+{
+       int err;
+
+       xe_device_mem_access_get(gt_to_xe(gt));
+       err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+       if (err)
+               goto out;
+
+       xe_gt_mcr_init(gt);
+       xe_pat_init(gt);
+
+       err = xe_uc_init(&gt->uc);
+       if (err)
+               goto out_fw;
+
+       err = xe_uc_init_hwconfig(&gt->uc);
+       if (err)
+               goto out_fw;
+
+       /* XXX: Fake that we pull the engine mask from hwconfig blob */
+       gt->info.engine_mask = gt->info.__engine_mask;
+
+out_fw:
+       xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
+out:
+       xe_device_mem_access_put(gt_to_xe(gt));
+
+       return err;
+}
+
 int xe_gt_init(struct xe_gt *gt)
 {
        int err;

diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
index c1675bd44cf6d6b6e16d5b4da0fec7f0bd3c3dd4..ed6ea8057e35fe9fcf91022ad45b5c68648333f1 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt.h
+++ b/drivers/gpu/drm/xe/xe_gt.h
@@ -33,6 +33,7 @@ static inline bool xe_fault_inject_gt_reset(void)
 #endif
 
 struct xe_gt *xe_gt_alloc(struct xe_tile *tile);
+int xe_gt_init_hwconfig(struct xe_gt *gt);
 int xe_gt_init_early(struct xe_gt *gt);
 int xe_gt_init(struct xe_gt *gt);
 int xe_gt_record_default_lrcs(struct xe_gt *gt);

diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
index d62137306d280880394e5d95d5c3bbe5599f44ba..7033f8c1b4318a74bce0cfe75673c3eaf96e3a58 100644 (file)
--- a/drivers/gpu/drm/xe/xe_uc.c
+++ b/drivers/gpu/drm/xe/xe_uc.c
@@ -32,13 +32,15 @@ uc_to_xe(struct xe_uc *uc)
 /* Should be called once at driver load only */
 int xe_uc_init(struct xe_uc *uc)
 {
+       struct xe_device *xe = uc_to_xe(uc);
        int ret;
 
+       xe_device_mem_access_get(xe);
+
        /*
         * We call the GuC/HuC/GSC init functions even if GuC submission is off
         * to correctly move our tracking of the FW state to "disabled".
         */
-
        ret = xe_guc_init(&uc->guc);
        if (ret)
                goto err;
@@ -52,7 +54,7 @@ int xe_uc_init(struct xe_uc *uc)
                goto err;
 
        if (!xe_device_uc_enabled(uc_to_xe(uc)))
-               return 0;
+               goto err;
 
        ret = xe_wopcm_init(&uc->wopcm);
        if (ret)
@@ -66,9 +68,13 @@ int xe_uc_init(struct xe_uc *uc)
        if (ret)
                goto err;
 
+       xe_device_mem_access_put(xe);
+
        return 0;
 
 err:
+       xe_device_mem_access_put(xe);
+
        return ret;
 }