drm/i915: add gmch substruct to struct drm_i915_private

Group the GMCH related members together.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c10c8f16cb5d12041e009f788bd9810225d6962d.1673958757.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
index a69bfcac9a94542ae948030ed1dfb18a87c40b20..9cedeb8c2f4dc2174b9211d86596e47ac0d83750 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vga.c
+++ b/drivers/gpu/drm/i915/display/intel_vga.c
@@ -104,7 +104,7 @@ intel_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
        unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
        u16 gmch_ctrl;
 
-       if (pci_read_config_word(i915->bridge_dev, reg, &gmch_ctrl)) {
+       if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) {
                drm_err(&i915->drm, "failed to read control word\n");
                return -EIO;
        }
@@ -117,7 +117,7 @@ intel_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
        else
                gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
 
-       if (pci_write_config_word(i915->bridge_dev, reg, gmch_ctrl)) {
+       if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) {
                drm_err(&i915->drm, "failed to write control word\n");
                return -EIO;
        }

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
index 1c492eaee7d984960527acce6421186d6b3d2d5f..77c793812eb46a30c7b87b452ab097901ac35794 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
@@ -80,7 +80,7 @@ int intel_ggtt_gmch_probe(struct i915_ggtt *ggtt)
        phys_addr_t gmadr_base;
        int ret;
 
-       ret = intel_gmch_probe(i915->bridge_dev, to_pci_dev(i915->drm.dev), NULL);
+       ret = intel_gmch_probe(i915->gmch.pdev, to_pci_dev(i915->drm.dev), NULL);
        if (!ret) {
                drm_err(&i915->drm, "failed to set up gmch\n");
                return -EIO;

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index c1e427ba57ae5d95a41e84ab10d48e547ea781a9..59cbc24cda6ccc01d1dc873e98e5b9ad03dd7d86 100644 (file)
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -117,15 +117,15 @@ static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 {
        int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
 
-       dev_priv->bridge_dev =
+       dev_priv->gmch.pdev =
                pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
-       if (!dev_priv->bridge_dev) {
+       if (!dev_priv->gmch.pdev) {
                drm_err(&dev_priv->drm, "bridge device not found\n");
                return -EIO;
        }
 
        return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev,
-                                       dev_priv->bridge_dev);
+                                       dev_priv->gmch.pdev);
 }
 
 /* Allocate space for the MCH regs if needed, return nonzero on error */
@@ -138,8 +138,8 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
        int ret;
 
        if (GRAPHICS_VER(dev_priv) >= 4)
-               pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
-       pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
+               pci_read_config_dword(dev_priv->gmch.pdev, reg + 4, &temp_hi);
+       pci_read_config_dword(dev_priv->gmch.pdev, reg, &temp_lo);
        mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 
        /* If ACPI doesn't have it, assume we need to allocate it ourselves */
@@ -150,26 +150,26 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 #endif
 
        /* Get some space for it */
-       dev_priv->mch_res.name = "i915 MCHBAR";
-       dev_priv->mch_res.flags = IORESOURCE_MEM;
-       ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
-                                    &dev_priv->mch_res,
+       dev_priv->gmch.mch_res.name = "i915 MCHBAR";
+       dev_priv->gmch.mch_res.flags = IORESOURCE_MEM;
+       ret = pci_bus_alloc_resource(dev_priv->gmch.pdev->bus,
+                                    &dev_priv->gmch.mch_res,
                                     MCHBAR_SIZE, MCHBAR_SIZE,
                                     PCIBIOS_MIN_MEM,
                                     0, pcibios_align_resource,
-                                    dev_priv->bridge_dev);
+                                    dev_priv->gmch.pdev);
        if (ret) {
                drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
-               dev_priv->mch_res.start = 0;
+               dev_priv->gmch.mch_res.start = 0;
                return ret;
        }
 
        if (GRAPHICS_VER(dev_priv) >= 4)
-               pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
-                                      upper_32_bits(dev_priv->mch_res.start));
+               pci_write_config_dword(dev_priv->gmch.pdev, reg + 4,
+                                      upper_32_bits(dev_priv->gmch.mch_res.start));
 
-       pci_write_config_dword(dev_priv->bridge_dev, reg,
-                              lower_32_bits(dev_priv->mch_res.start));
+       pci_write_config_dword(dev_priv->gmch.pdev, reg,
+                              lower_32_bits(dev_priv->gmch.mch_res.start));
        return 0;
 }
 
@@ -184,13 +184,13 @@ intel_setup_mchbar(struct drm_i915_private *dev_priv)
        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                return;
 
-       dev_priv->mchbar_need_disable = false;
+       dev_priv->gmch.mchbar_need_disable = false;
 
        if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
-               pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
+               pci_read_config_dword(dev_priv->gmch.pdev, DEVEN, &temp);
                enabled = !!(temp & DEVEN_MCHBAR_EN);
        } else {
-               pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
+               pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg, &temp);
                enabled = temp & 1;
        }
 
@@ -201,15 +201,15 @@ intel_setup_mchbar(struct drm_i915_private *dev_priv)
        if (intel_alloc_mchbar_resource(dev_priv))
                return;
 
-       dev_priv->mchbar_need_disable = true;
+       dev_priv->gmch.mchbar_need_disable = true;
 
        /* Space is allocated or reserved, so enable it. */
        if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
-               pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
+               pci_write_config_dword(dev_priv->gmch.pdev, DEVEN,
                                       temp | DEVEN_MCHBAR_EN);
        } else {
-               pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
-               pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
+               pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg, &temp);
+               pci_write_config_dword(dev_priv->gmch.pdev, mchbar_reg, temp | 1);
        }
 }
 
@@ -218,28 +218,28 @@ intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 {
        int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 
-       if (dev_priv->mchbar_need_disable) {
+       if (dev_priv->gmch.mchbar_need_disable) {
                if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
                        u32 deven_val;
 
-                       pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
+                       pci_read_config_dword(dev_priv->gmch.pdev, DEVEN,
                                              &deven_val);
                        deven_val &= ~DEVEN_MCHBAR_EN;
-                       pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
+                       pci_write_config_dword(dev_priv->gmch.pdev, DEVEN,
                                               deven_val);
                } else {
                        u32 mchbar_val;
 
-                       pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
+                       pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg,
                                              &mchbar_val);
                        mchbar_val &= ~1;
-                       pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
+                       pci_write_config_dword(dev_priv->gmch.pdev, mchbar_reg,
                                               mchbar_val);
                }
        }
 
-       if (dev_priv->mch_res.start)
-               release_resource(&dev_priv->mch_res);
+       if (dev_priv->gmch.mch_res.start)
+               release_resource(&dev_priv->gmch.mch_res);
 }
 
 static int i915_workqueues_init(struct drm_i915_private *dev_priv)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2a6e212f882445a12b0ea1ed0f82195230ed430a..902ca4747e0afbfbe39ad607c64c3ab765ecaacf 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -216,13 +216,15 @@ struct drm_i915_private {
 
        struct intel_gvt *gvt;
 
-       struct pci_dev *bridge_dev;
+       struct {
+               struct pci_dev *pdev;
+               struct resource mch_res;
+               bool mchbar_need_disable;
+       } gmch;
 
        struct rb_root uabi_engines;
        unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
 
-       struct resource mch_res;
-
        /* protects the irq masks */
        spinlock_t irq_lock;
 
@@ -268,8 +270,6 @@ struct drm_i915_private {
 
        struct i915_gem_mm mm;
 
-       bool mchbar_need_disable;
-
        struct intel_l3_parity l3_parity;
 
        /*