drm/amdgpu: Use the correct API to read register

Use SOC15 API so that the register offset is calculated correctly.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 2676a185c232d03caee6446f02eb3b206f108c3a..ad3e8cefbdb27a2884ba23c0db8a22f81b97f2b6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -1637,7 +1637,7 @@ static int gfx_v9_4_3_mqd_init(struct amdgpu_ring *ring)
 
        /* set static priority for a queue/ring */
        gfx_v9_4_3_mqd_set_priority(ring, mqd);
-       mqd->cp_hqd_quantum = RREG32(regCP_HQD_QUANTUM);
+       mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, regCP_HQD_QUANTUM);
 
        /* map_queues packet doesn't need activate the queue,
         * so only kiq need set this field.