if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
u32 ddcc_status = 0;
+ u32 mult = 1;
- if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
+ if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11)
+ mult = GEN9_FREQ_SCALER;
+ if (snb_pcode_read(rps_to_gt(rps)->uncore,
+ HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
&ddcc_status, NULL) == 0)
rps->efficient_freq =
- clamp_t(u8,
- (ddcc_status >> 8) & 0xff,
+ clamp_t(u32,
+ ((ddcc_status >> 8) & 0xff) * mult,
rps->min_freq,
rps->max_freq);
}
.has_4tile = 1, \
.has_64k_pages = 1, \
.has_guc_deprivilege = 1, \
+ .has_heci_pxp = 1, \
.needs_compact_pt = 1, \
+ .has_media_ratio_mode = 1, \
.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
BIT(VECS0) | BIT(VECS1) | \
- BIT(VCS0) | BIT(VCS2)
+ BIT(VCS0) | BIT(VCS2) | \
+ BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
- __maybe_unused
static const struct intel_device_info dg2_info = {
DG2_FEATURES,
XE_LPD_FEATURES,
goto err_rpm;
}
- work->vm = i915_vm_get(vma->vm);
+ work->vm = vma->vm;
+
- moving = i915_gem_object_get_moving_fence(vma->obj);
++ err = i915_gem_object_get_moving_fence(vma->obj, &moving);
++ if (err)
++ goto err_rpm;
+
dma_fence_work_chain(&work->base, moving);
/* Allocate enough page directories to used PTE */