]> git.dujemihanovic.xyz Git - linux.git/commitdiff
can: m_can: pci: fix incorrect reference clock rate
authorMatthias Schiffer <matthias.schiffer@ew.tq-group.com>
Mon, 15 Nov 2021 09:18:49 +0000 (10:18 +0100)
committerMarc Kleine-Budde <mkl@pengutronix.de>
Tue, 7 Dec 2021 08:51:41 +0000 (09:51 +0100)
When testing the CAN controller on our Ekhart Lake hardware, we
determined that all communication was running with twice the configured
bitrate. Changing the reference clock rate from 100MHz to 200MHz fixed
this. Intel's support has confirmed to us that 200MHz is indeed the
correct clock rate.

Fixes: cab7ffc0324f ("can: m_can: add PCI glue driver for Intel Elkhart Lake")
Link: https://lore.kernel.org/all/c9cf3995f45c363e432b3ae8eb1275e54f009fc8.1636967198.git.matthias.schiffer@ew.tq-group.com
Cc: stable@vger.kernel.org
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
drivers/net/can/m_can/m_can_pci.c

index d72c294ac4d3356cdb8d988c9093f743366c260a..8f184a852a0a7c7476eaa1cf231ab1e4d46a5dc0 100644 (file)
@@ -18,7 +18,7 @@
 
 #define M_CAN_PCI_MMIO_BAR             0
 
-#define M_CAN_CLOCK_FREQ_EHL           100000000
+#define M_CAN_CLOCK_FREQ_EHL           200000000
 #define CTL_CSR_INT_CTL_OFFSET         0x508
 
 struct m_can_pci_priv {