drm/amd/pm: fix the pp_dpm_pcie issue on smu v14.0.2/3

fix the pp_dpm_pcie issue on smu v14.0.2/3 as below:
0: 2.5GT/s, x4 250Mhz
1: 8.0GT/s, x4 616Mhz *
2: 8.0GT/s, x4 1143Mhz *
the middle level can be removed since it is always skipped on
smu v14.0.2/3

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit fedf6db3ea9dc5eda0b78cfbbb8f7a88b97e5b24)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index 514151e3e6661b9105a713203e8f9b1ada2f501a..2b45adecbed2e54e9b6cb35dba4e35a99e874c1f 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -683,6 +683,9 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu)
                pcie_table->clk_freq[pcie_table->num_of_link_levels] =
                                        skutable->LclkFreq[link_level];
                pcie_table->num_of_link_levels++;
+
+               if (link_level == 0)
+                       link_level++;
        }
 
        /* dcefclk dpm table setup */