drm/amdgpu/gfx9.4.3: set additional bits on MEC halt

Need to set the pipe reset and cache invalidation bits
on halt otherwise we can get stale state if the CP firmware
changes (e.g., on module unload and reload).

Tested-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index b940d2ad57dba6682507d957cb975d2c1905b950..611659404703d9d5b31dfe37bb4f9a13457f85ab 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -1701,7 +1701,15 @@ static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev,
                WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);
        } else {
                WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,
-                       (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
+                       (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK |
+                        CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK |
+                        CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK |
+                        CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK |
+                        CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK |
+                        CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK |
+                        CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK |
+                        CP_MEC_CNTL__MEC_ME1_HALT_MASK |
+                        CP_MEC_CNTL__MEC_ME2_HALT_MASK));
                adev->gfx.kiq[xcc_id].ring.sched.ready = false;
        }
        udelay(50);