drm/i915/pvc: Add SSEU changes

PVC splits the mask of enabled DSS over two registers.  It also changes
the meaning of the EU fuse register such that each bit represents a
single EU rather than a pair of EUs.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-7-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 58e9b464d564cd0e29a0a29496e4ef514d95b844..6aa1ceaa8d271244ca0f69c374affca25d8c7ba9 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -561,6 +561,7 @@
 #define   GEN11_GT_VEBOX_DISABLE_MASK          (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
 
 #define GEN12_GT_COMPUTE_DSS_ENABLE            _MMIO(0x9144)
+#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT                _MMIO(0x9148)
 
 #define GEN6_UCGCTL1                           _MMIO(0x9400)
 #define   GEN6_GAMUNIT_CLOCK_GATE_DISABLE      (1 << 22)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 826d11f18817aa7639ed98714acfa81bd5d8602d..7ef75f0d9c9e0b840a297cfb134ba313a3b44fd2 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -210,27 +210,44 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
        struct intel_uncore *uncore = gt->uncore;
        u16 eu_en = 0;
        u8 eu_en_fuse;
+       int num_compute_regs, num_geometry_regs;
        int eu;
 
+       if (IS_PONTEVECCHIO(gt->i915)) {
+               num_geometry_regs = 0;
+               num_compute_regs = 2;
+       } else {
+               num_geometry_regs = 1;
+               num_compute_regs = 1;
+       }
+
        /*
         * The concept of slice has been removed in Xe_HP.  To be compatible
         * with prior generations, assume a single slice across the entire
         * device. Then calculate out the DSS for each workload type within
         * that software slice.
         */
-       intel_sseu_set_info(sseu, 1, 32, 16);
+       intel_sseu_set_info(sseu, 1,
+                           32 * max(num_geometry_regs, num_compute_regs),
+                           16);
        sseu->has_xehp_dss = 1;
 
-       xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+       xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,
+                          num_geometry_regs,
                           GEN12_GT_GEOMETRY_DSS_ENABLE);
-       xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
-                          GEN12_GT_COMPUTE_DSS_ENABLE);
+       xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask,
+                          num_compute_regs,
+                          GEN12_GT_COMPUTE_DSS_ENABLE,
+                          XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
 
        eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
 
-       for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
-               if (eu_en_fuse & BIT(eu))
-                       eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+       if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915))
+               eu_en = eu_en_fuse;
+       else
+               for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+                       if (eu_en_fuse & BIT(eu))
+                               eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
 
        xehp_compute_sseu_info(sseu, eu_en);
 }

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index f0e09b743faaa6fca355b76a5a6345a3e8dbd70f..aa87d3832d60d92539413d6cc5f840873c65696a 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -33,7 +33,7 @@ struct drm_printer;
  * Maximum number of 32-bit registers used by hardware to express the
  * enabled/disabled subslices.
  */
-#define I915_MAX_SS_FUSE_REGS  1
+#define I915_MAX_SS_FUSE_REGS  2
 #define I915_MAX_SS_FUSE_BITS  (I915_MAX_SS_FUSE_REGS * 32)
 
 /* Maximum number of EUs that can exist within a subslice or DSS. */

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ec1b3484fdafa1cd8fa06e18fe48260726ec3bf2..fbea4d1ede7c85f28e431035dac134c10643c635 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1422,6 +1422,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_3D_PIPELINE(i915)  (INTEL_INFO(i915)->has_3d_pipeline)
 
+#define HAS_ONE_EU_PER_FUSE_BIT(i915)  (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
+
 /* i915_gem.c */
 void i915_gem_init_early(struct drm_i915_private *dev_priv);
 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 269d7c8f2f81d6bf5ab68c7a1d6967c9be3a9048..177aefa6511e68e8c3cd8328607bc5fe07cd7592 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1090,7 +1090,8 @@ static const struct intel_device_info ats_m_info = {
        XE_HP_FEATURES, \
        .dma_mask_size = 52, \
        .has_3d_pipeline = 0, \
-       .has_l3_ccs_read = 1
+       .has_l3_ccs_read = 1, \
+       .has_one_eu_per_fuse_bit = 1
 
 __maybe_unused
 static const struct intel_device_info pvc_info = {

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4e1c80966ab56216305f0d03629b039973891cd9..346f17f2dce8c1a114152a08f11fce17720cef18 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -158,6 +158,7 @@ enum intel_ppgtt_type {
        func(has_logical_ring_elsq); \
        func(has_media_ratio_mode); \
        func(has_mslices); \
+       func(has_one_eu_per_fuse_bit); \
        func(has_pooled_eu); \
        func(has_pxp); \
        func(has_rc6); \