#define IS_AST_GEN6(__ast) __ast_gen_is_eq(__ast, 6)
#define IS_AST_GEN7(__ast) __ast_gen_is_eq(__ast, 7)
-#define AST_IO_AR_PORT_WRITE (0x40)
+#define AST_IO_VGAARI_W (0x40)
#define AST_IO_MISC_PORT_WRITE (0x42)
#define AST_IO_VGA_ENABLE_PORT (0x43)
#define AST_IO_SEQ_PORT (0x44)
jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
for (i = 0; i < 20; i++) {
jreg = stdtable->ar[i];
- ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
- ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
+ ast_io_write8(ast, AST_IO_VGAARI_W, (u8)i);
+ ast_io_write8(ast, AST_IO_VGAARI_W, jreg);
}
- ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
- ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
+ ast_io_write8(ast, AST_IO_VGAARI_W, 0x14);
+ ast_io_write8(ast, AST_IO_VGAARI_W, 0x00);
jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
- ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
+ ast_io_write8(ast, AST_IO_VGAARI_W, 0x20);
/* Set GR */
for (i = 0; i < 9; i++)