drm/amdgpu/mes12: switch SET_SHADER_DEBUGGER pkt to mes schq pipe

The SET_SHADER_DEBUGGER packet must work with the added
hardware queue, switch the packet submitting to mes schq pipe.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.11.x

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index e499b2857a01e1d2a5635b10133f6da0b6a2d5ea..ef05a411623060a7a89e4ad32a6332dfabeacf99 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -479,6 +479,11 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
        union MESAPI__MISC misc_pkt;
        int pipe;
 
+       if (mes->adev->enable_uni_mes)
+               pipe = AMDGPU_MES_KIQ_PIPE;
+       else
+               pipe = AMDGPU_MES_SCHED_PIPE;
+
        memset(&misc_pkt, 0, sizeof(misc_pkt));
 
        misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
@@ -513,6 +518,7 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
                misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
                break;
        case MES_MISC_OP_SET_SHADER_DEBUGGER:
+               pipe = AMDGPU_MES_SCHED_PIPE;
                misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
                misc_pkt.set_shader_debugger.process_context_addr =
                                input->set_shader_debugger.process_context_addr;
@@ -530,11 +536,6 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
                return -EINVAL;
        }
 
-       if (mes->adev->enable_uni_mes)
-               pipe = AMDGPU_MES_KIQ_PIPE;
-       else
-               pipe = AMDGPU_MES_SCHED_PIPE;
-
        return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
                        &misc_pkt, sizeof(misc_pkt),
                        offsetof(union MESAPI__MISC, api_status));