arm64: dts: mediatek: mt2712: fix validation errors

1. Fixup infracfg clock controller binding
   It also acts as reset controller so #reset-cells is required.
2. Use -pins suffix for pinctrl

This fixes:
arch/arm64/boot/dts/mediatek/mt2712-evb.dtb: syscon@10001000: '#reset-cells' is a required property
        from schema $id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
arch/arm64/boot/dts/mediatek/mt2712-evb.dtb: pinctrl@1000b000: 'eth_default', 'eth_sleep', 'usb0_iddig', 'usb1_iddig' do not match any of the regexes: 'pinctrl-[0-9]+', 'pins$'
        from schema $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240301074741.8362-1-zajec5@gmail.com
[Angelo: Added Fixes tags]
Fixes: 5d4839709c8e ("arm64: dts: mt2712: Add clock controller device nodes")
Fixes: 1724f4cc5133 ("arm64: dts: Add USB3 related nodes for MT2712")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 0c38f7b51763776cda640ab73f8513f4cce9f1e5..234e3b23d7a8d3206c1f5e74f875a4501eea3942 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -129,7 +129,7 @@
 };
 
 &pio {
-       eth_default: eth_default {
+       eth_default: eth-default-pins {
                tx_pins {
                        pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
                                 <MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
@@ -156,7 +156,7 @@
                };
        };
 
-       eth_sleep: eth_sleep {
+       eth_sleep: eth-sleep-pins {
                tx_pins {
                        pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
                                 <MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
@@ -182,14 +182,14 @@
                };
        };
 
-       usb0_id_pins_float: usb0_iddig {
+       usb0_id_pins_float: usb0-iddig-pins {
                pins_iddig {
                        pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
                        bias-pull-up;
                };
        };
 
-       usb1_id_pins_float: usb1_iddig {
+       usb1_id_pins_float: usb1-iddig-pins {
                pins_iddig {
                        pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
                        bias-pull-up;

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 6d218caa198cfd304eb546988737b1dc261c34ed..082672efba0a3408e9a9bb47ffad26046f97c3a2 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -249,10 +249,11 @@
                #clock-cells = <1>;
        };
 
-       infracfg: syscon@10001000 {
+       infracfg: clock-controller@10001000 {
                compatible = "mediatek,mt2712-infracfg", "syscon";
                reg = <0 0x10001000 0 0x1000>;
                #clock-cells = <1>;
+               #reset-cells = <1>;
        };
 
        pericfg: syscon@10003000 {