DONOTMERGE: Enable AArch64 system timer properly

With this, an initramfs can be reached.

Long-term, this will be moved someplace such as U-Boot.

diff --git a/drivers/clk/mmp/clk-of-pxa1908.c b/drivers/clk/mmp/clk-of-pxa1908.c
index 753dd031b147cdbbdf69e4b58a3407ef9b5e97c8..4c9580f9efa1c2cb517a559e9c6d1103adc32281 100644 (file)
--- a/drivers/clk/mmp/clk-of-pxa1908.c
+++ b/drivers/clk/mmp/clk-of-pxa1908.c
@@ -31,6 +31,7 @@
 #define APBC_TWSI1             0x60
 #define APBC_THERMAL           0x6c
 #define APBC_TWSI3             0x70
+#define APBC_COUNTER_CLK_SEL   0x64
 
 #define APBCP_UART2            0x1c
 #define APBCP_TWSI2            0x28
@@ -261,6 +262,23 @@ static void __init pxa1908_apbc_clk_init(struct device_node *np)
        mmp_clk_init(np, &pxa_unit->unit, APBC_NR_CLKS);
 
        pxa1908_apb_periph_clk_init(pxa_unit);
+
+       /* Assign a 26MHz clock to the ARM architected timer. */
+       int tmp = readl(pxa_unit->apbc_base + APBC_COUNTER_CLK_SEL);
+       if ((tmp >> 16) == 0x319) {
+               writel(tmp | 1, pxa_unit->apbc_base + APBC_COUNTER_CLK_SEL);
+       }
+
+       /* Enable the ARM architected timer. */
+       void __iomem *cnt_base = ioremap(0xd4101000, 0x1000);
+       if (!cnt_base)
+               pr_err("failed to map cnt register\n");
+       else {
+               writel(BIT(0) | BIT(1), cnt_base);
+               iounmap(cnt_base);
+       }
+
+       pr_notice("apbc ready\n");
 }
 CLK_OF_DECLARE(pxa1908_apbc, "marvell,pxa1908-apbc", pxa1908_apbc_clk_init);