drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL

Track the system agent voltage we request from pcode in the cdclk state
on SKL/KBL/CFL. Annoyingly we can't actually read out the current value since
there's no pcode command to do that, so we'll have to just assume that
it worked.

v2: s/voltage/voltage_level/ (Rodrigo)

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-6-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index c98fec333dd1faa5062745b7ce80414a753a92da..38e31df265bdadcd39fad054e34a352bca41f429 100644 (file)
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -785,6 +785,24 @@ static int skl_calc_cdclk(int min_cdclk, int vco)
        }
 }
 
+static u8 skl_calc_voltage_level(int cdclk)
+{
+       switch (cdclk) {
+       default:
+       case 308571:
+       case 337500:
+               return 0;
+       case 450000:
+       case 432000:
+               return 1;
+       case 540000:
+               return 2;
+       case 617143:
+       case 675000:
+               return 3;
+       }
+}
+
 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
                             struct intel_cdclk_state *cdclk_state)
 {
@@ -835,7 +853,7 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv,
        cdclk_state->cdclk = cdclk_state->ref;
 
        if (cdclk_state->vco == 0)
-               return;
+               goto out;
 
        cdctl = I915_READ(CDCLK_CTL);
 
@@ -876,6 +894,14 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv,
                        break;
                }
        }
+
+ out:
+       /*
+        * Can't read this out :( Let's assume it's
+        * at least what the CDCLK frequency requires.
+        */
+       cdclk_state->voltage_level =
+               skl_calc_voltage_level(cdclk_state->cdclk);
 }
 
 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
@@ -960,7 +986,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 {
        int cdclk = cdclk_state->cdclk;
        int vco = cdclk_state->vco;
-       u32 freq_select, pcu_ack;
+       u32 freq_select;
        int ret;
 
        mutex_lock(&dev_priv->pcu_lock);
@@ -984,21 +1010,17 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
        case 308571:
        case 337500:
                freq_select = CDCLK_FREQ_337_308;
-               pcu_ack = 0;
                break;
        case 450000:
        case 432000:
                freq_select = CDCLK_FREQ_450_432;
-               pcu_ack = 1;
                break;
        case 540000:
                freq_select = CDCLK_FREQ_540;
-               pcu_ack = 2;
                break;
        case 617143:
        case 675000:
                freq_select = CDCLK_FREQ_675_617;
-               pcu_ack = 3;
                break;
        }
 
@@ -1014,7 +1036,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 
        /* inform PCU of the change */
        mutex_lock(&dev_priv->pcu_lock);
-       sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
+       sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+                               cdclk_state->voltage_level);
        mutex_unlock(&dev_priv->pcu_lock);
 
        intel_update_cdclk(dev_priv);
@@ -1093,6 +1116,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
        if (cdclk_state.vco == 0)
                cdclk_state.vco = 8100000;
        cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
+       cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
 
        skl_set_cdclk(dev_priv, &cdclk_state);
 }
@@ -1110,6 +1134,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
        cdclk_state.cdclk = cdclk_state.ref;
        cdclk_state.vco = 0;
+       cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
 
        skl_set_cdclk(dev_priv, &cdclk_state);
 }
@@ -1968,12 +1993,16 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
 
        intel_state->cdclk.logical.vco = vco;
        intel_state->cdclk.logical.cdclk = cdclk;
+       intel_state->cdclk.logical.voltage_level =
+               skl_calc_voltage_level(cdclk);
 
        if (!intel_state->active_crtcs) {
                cdclk = skl_calc_cdclk(0, vco);
 
                intel_state->cdclk.actual.vco = vco;
                intel_state->cdclk.actual.cdclk = cdclk;
+               intel_state->cdclk.actual.voltage_level =
+                       skl_calc_voltage_level(cdclk);
        } else {
                intel_state->cdclk.actual =
                        intel_state->cdclk.logical;