if (ret)
goto err_fsgen;
- ret = rx_macro_register_mclk_output(rx);
- if (ret)
- goto err_clkout;
-
ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv,
rx_macro_dai,
ARRAY_SIZE(rx_macro_dai));
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
+ ret = rx_macro_register_mclk_output(rx);
+ if (ret)
+ goto err_clkout;
+
return 0;
err_clkout:
if (ret)
goto err_fsgen;
- ret = tx_macro_register_mclk_output(tx);
- if (ret)
- goto err_clkout;
-
ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv,
tx_macro_dai,
ARRAY_SIZE(tx_macro_dai));
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
+ ret = tx_macro_register_mclk_output(tx);
+ if (ret)
+ goto err_clkout;
+
return 0;
err_clkout:
if (ret)
goto err_mclk;
- ret = va_macro_register_fsgen_output(va);
- if (ret)
- goto err_clkout;
-
- va->fsgen = clk_hw_get_clk(&va->hw, "fsgen");
- if (IS_ERR(va->fsgen)) {
- ret = PTR_ERR(va->fsgen);
- goto err_clkout;
- }
-
if (va->has_swr_master) {
/* Set default CLK div to 1 */
regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0,
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
+ ret = va_macro_register_fsgen_output(va);
+ if (ret)
+ goto err_clkout;
+
+ va->fsgen = clk_hw_get_clk(&va->hw, "fsgen");
+ if (IS_ERR(va->fsgen)) {
+ ret = PTR_ERR(va->fsgen);
+ goto err_clkout;
+ }
+
return 0;
err_clkout:
if (ret)
goto err_fsgen;
- ret = wsa_macro_register_mclk_output(wsa);
- if (ret)
- goto err_clkout;
-
-
ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv,
wsa_macro_dai,
ARRAY_SIZE(wsa_macro_dai));
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
+ ret = wsa_macro_register_mclk_output(wsa);
+ if (ret)
+ goto err_clkout;
+
return 0;
err_clkout: