drm/amd/display: Update IPS default mode for DCN35/DCN351

[WHY]
RCG state of IPX in idle is more stable for DCN351 and some variants of
DCN35 than IPS2.

[HOW]
Rework dm_get_default_ips_mode() to specify default per ASIC and update
DCN35/DCN351 defaults accordingly.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Sun peng Li <sunpeng.li@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 08bcb47d70743137b4832de5db512625859841aa..94c8d9966ec387e0b5f7aa460b8dea45d7ab1ef4 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1771,25 +1771,41 @@ static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *
 static enum dmub_ips_disable_type dm_get_default_ips_mode(
        struct amdgpu_device *adev)
 {
-       /*
-        * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to
-        * cause a hard hang. A fix exists for newer PMFW.
-        *
-        * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest
-        * IPS state in all cases, except for s0ix and all displays off (DPMS),
-        * where IPS2 is allowed.
-        *
-        * When checking pmfw version, use the major and minor only.
-        */
-       if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 5, 0) &&
-           (adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)
-               return DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
+       enum dmub_ips_disable_type ret = DMUB_IPS_ENABLE;
 
-       if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0))
-               return DMUB_IPS_ENABLE;
+       switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
+       case IP_VERSION(3, 5, 0):
+               /*
+                * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to
+                * cause a hard hang. A fix exists for newer PMFW.
+                *
+                * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest
+                * IPS state in all cases, except for s0ix and all displays off (DPMS),
+                * where IPS2 is allowed.
+                *
+                * When checking pmfw version, use the major and minor only.
+                */
+               if ((adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)
+                       ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
+               else if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(11, 5, 0))
+                       /*
+                        * Other ASICs with DCN35 that have residency issues with
+                        * IPS2 in idle.
+                        * We want them to use IPS2 only in display off cases.
+                        */
+                       ret =  DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
+               break;
+       case IP_VERSION(3, 5, 1):
+               ret =  DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
+               break;
+       default:
+               /* ASICs older than DCN35 do not have IPSs */
+               if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0))
+                       ret = DMUB_IPS_DISABLE_ALL;
+               break;
+       }
 
-       /* ASICs older than DCN35 do not have IPSs */
-       return DMUB_IPS_DISABLE_ALL;
+       return ret;
 }
 
 static int amdgpu_dm_init(struct amdgpu_device *adev)