drm/i915/selftests: Skip poisoning SET_PREDICATE_RESULT on dg2

When predication is enabled all commands baring a few (such as MI_BB_END)
are nop'ed. If we accidentally enable predication while poisoning the
context, not only is the rest of the poisoning skipped (thus disabling
the test), but the closing instructions of the poison request are
nop'ed. Not only do we then not signal the waiting context, but we even
prevent re-enabling arbitration and the GPU will not perform a context
switch at the end of the request.

Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Suggested-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220425152317.4275-3-ramalingam.c@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 594a629cb28f196e6e3f2a047691cdd4f5d81b76..1dab554bf640946734106031e142b98a547c3a87 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -193,6 +193,7 @@
 #define RING_TIMESTAMP_UDW(base)               _MMIO((base) + 0x358 + 4)
 #define RING_CONTEXT_STATUS_PTR(base)          _MMIO((base) + 0x3a0)
 #define RING_CTX_TIMESTAMP(base)               _MMIO((base) + 0x3a8) /* gen8+ */
+#define RING_PREDICATE_RESULT(base)            _MMIO((base) + 0x3b8)
 #define RING_FORCE_TO_NONPRIV(base, i)         _MMIO(((base) + 0x4D0) + (i) * 4)
 #define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK   REG_GENMASK(25, 2)
 #define   RING_FORCE_TO_NONPRIV_ACCESS_RW      (0 << 28)    /* CFL+ & Gen11+ */

diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 8dc7b88cdca00468c8ba6756b4f8a08e5f65da99..8b2c11dbe354f604b99779acafc1ef9b1571ae5b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -945,6 +945,19 @@ create_user_vma(struct i915_address_space *vm, unsigned long size)
        return vma;
 }
 
+static u32 safe_poison(u32 offset, u32 poison)
+{
+       /*
+        * Do not enable predication as it will nop all subsequent commands,
+        * not only disabling the tests (by preventing all the other SRM) but
+        * also preventing the arbitration events at the end of the request.
+        */
+       if (offset == i915_mmio_reg_offset(RING_PREDICATE_RESULT(0)))
+               poison &= ~REG_BIT(0);
+
+       return poison;
+}
+
 static struct i915_vma *
 store_context(struct intel_context *ce, struct i915_vma *scratch)
 {
@@ -1154,7 +1167,9 @@ static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
                *cs++ = MI_LOAD_REGISTER_IMM(len);
                while (len--) {
                        *cs++ = hw[dw];
-                       *cs++ = poison;
+                       *cs++ = safe_poison(hw[dw] & get_lri_mask(ce->engine,
+                                                                 MI_LRI_LRM_CS_MMIO),
+                                           poison);
                        dw += 2;
                }
        } while (dw < PAGE_SIZE / sizeof(u32) &&