Add a module parameter to override the partition mode.
Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
extern int amdgpu_vcnfw_log;
extern int amdgpu_sg_display;
+extern uint amdgpu_user_partt_mode;
+
#define AMDGPU_VM_MAX_NUM_CTX 4096
#define AMDGPU_SG_THRESHOLD (256*1024*1024)
#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
int amdgpu_use_xgmi_p2p = 1;
int amdgpu_vcnfw_log;
int amdgpu_sg_display = -1; /* auto */
+uint amdgpu_user_partt_mode;
static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
"specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
+/**
+ * DOC: partition_mode (int)
+ * Used to override the default SPX mode.
+ */
+MODULE_PARM_DESC(user_partt_mode,
+ "specify partition mode to be used (0 = AMDGPU_SPX_PARTITION_MODE(default value), \
+ 1 = AMDGPU_DPX_PARTITION_MODE, \
+ 2 = AMDGPU_TPX_PARTITION_MODE, \
+ 3 = AMDGPU_QPX_PARTITION_MODE, \
+ 4 = AMDGPU_CPX_PARTITION_MODE)");
+module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
+
/* These devices are not supported by amdgpu.
* They are supported by the mach64, r128, radeon drivers
*/
/* hardcode in emulation phase */
adev->gfx.num_xcd = 1;
- adev->gfx.num_xcc_per_xcp = 1;
- adev->gfx.partition_mode = AMDGPU_SPX_PARTITION_MODE;
+
+ adev->gfx.partition_mode = amdgpu_user_partt_mode;
+ /* calculate the num_xcc_in_xcp for the partition mode*/
+ switch (amdgpu_user_partt_mode) {
+ case AMDGPU_SPX_PARTITION_MODE:
+ adev->gfx.num_xcc_per_xcp = adev->gfx.num_xcd;
+ break;
+ case AMDGPU_DPX_PARTITION_MODE:
+ adev->gfx.num_xcc_per_xcp = adev->gfx.num_xcd / 2;
+ break;
+ case AMDGPU_TPX_PARTITION_MODE:
+ adev->gfx.num_xcc_per_xcp = adev->gfx.num_xcd / 3;
+ break;
+ case AMDGPU_QPX_PARTITION_MODE:
+ adev->gfx.num_xcc_per_xcp = adev->gfx.num_xcd / 4;
+ break;
+ case AMDGPU_CPX_PARTITION_MODE:
+ adev->gfx.num_xcc_per_xcp = 1;
+ break;
+ default:
+ adev->gfx.num_xcc_per_xcp = adev->gfx.num_xcd;
+ break;
+ }
adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
AMDGPU_MAX_COMPUTE_RINGS);