From 139ff3be23b7b78d13ddff17854ad83d896c6a51 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 14 May 2021 21:34:27 -0400 Subject: [PATCH] ppc: Remove MPC8315ERDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_MPC8315 platform, remove that support as well. Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc83xx/Kconfig | 14 - arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 3 +- arch/powerpc/cpu/mpc83xx/speed.c | 41 +- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 3 +- arch/powerpc/include/asm/global_data.h | 5 +- arch/powerpc/include/asm/immap_83xx.h | 45 --- arch/powerpc/include/asm/mpc8xxx_spi.h | 1 - board/freescale/mpc8315erdb/Kconfig | 12 - board/freescale/mpc8315erdb/MAINTAINERS | 7 - board/freescale/mpc8315erdb/Makefile | 6 - board/freescale/mpc8315erdb/README | 105 ------ board/freescale/mpc8315erdb/mpc8315erdb.c | 249 ------------- board/freescale/mpc8315erdb/sdram.c | 115 ------ configs/MPC8315ERDB_defconfig | 156 -------- include/configs/MPC8315ERDB.h | 370 ------------------- include/mpc83xx.h | 39 +- 16 files changed, 11 insertions(+), 1160 deletions(-) delete mode 100644 board/freescale/mpc8315erdb/Kconfig delete mode 100644 board/freescale/mpc8315erdb/MAINTAINERS delete mode 100644 board/freescale/mpc8315erdb/Makefile delete mode 100644 board/freescale/mpc8315erdb/README delete mode 100644 board/freescale/mpc8315erdb/mpc8315erdb.c delete mode 100644 board/freescale/mpc8315erdb/sdram.c delete mode 100644 configs/MPC8315ERDB_defconfig delete mode 100644 include/configs/MPC8315ERDB.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index a67216a2f4..d1b774f8d5 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -8,11 +8,6 @@ choice prompt "Target select" optional -config TARGET_MPC8315ERDB - bool "Support MPC8315ERDB" - select ARCH_MPC8315 - select BOARD_EARLY_INIT_F - config TARGET_MPC8323ERDB bool "Support MPC8323ERDB" select ARCH_MPC832X @@ -175,14 +170,6 @@ config ARCH_MPC8313 select MPC83XX_SECOND_I2C_SUPPORT select FSL_ELBC -config ARCH_MPC8315 - bool - select ARCH_MPC831X - select MPC83XX_PCIE1_SUPPORT - select MPC83XX_PCIE2_SUPPORT - select MPC83XX_SATA_SUPPORT - select FSL_ELBC - config ARCH_MPC832X bool select MPC83XX_QUICC_ENGINE @@ -265,7 +252,6 @@ endmenu config FSL_ELBC bool -source "board/freescale/mpc8315erdb/Kconfig" source "board/freescale/mpc8323erdb/Kconfig" source "board/freescale/mpc832xemds/Kconfig" source "board/freescale/mpc8349emds/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig index c657a47b11..75ec9c9a34 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig @@ -19,7 +19,7 @@ config DDR_MC_CLOCK_MODE_1_2 bool "1 : 2" config DDR_MC_CLOCK_MODE_1_1 - depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X bool "1 : 1" endchoice @@ -143,7 +143,6 @@ config CORE_PLL_VCO_DIVIDER_4 bool "4" config CORE_PLL_VCO_DIVIDER_8 - depends on !ARCH_MPC8315 bool "8" endchoice diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 58e197f120..e5db96b328 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -104,9 +104,6 @@ int get_clocks(void) #if !defined(CONFIG_ARCH_MPC832X) u32 i2c2_clk; #endif -#if defined(CONFIG_ARCH_MPC8315) - u32 tdm_clk; -#endif #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif @@ -130,7 +127,7 @@ int get_clocks(void) u32 pciexp1_clk; u32 pciexp2_clk; #endif -#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) u32 sata_clk; #endif @@ -200,8 +197,8 @@ int get_clocks(void) } #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC834X) || \ + defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -294,25 +291,6 @@ int get_clocks(void) return -8; } #endif -#if defined(CONFIG_ARCH_MPC8315) - switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) { - case 0: - tdm_clk = 0; - break; - case 1: - tdm_clk = csb_clk; - break; - case 2: - tdm_clk = csb_clk / 2; - break; - case 3: - tdm_clk = csb_clk / 3; - break; - default: - /* unknown SCCR_TDMCM value */ - return -8; - } -#endif #if defined(CONFIG_ARCH_MPC834X) i2c1_clk = tsec2_clk; @@ -372,7 +350,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { case 0: sata_clk = 0; @@ -462,9 +440,6 @@ int get_clocks(void) #if defined(CONFIG_ARCH_MPC834X) gd->arch.usbmph_clk = usbmph_clk; #endif -#if defined(CONFIG_ARCH_MPC8315) - gd->arch.tdm_clk = tdm_clk; -#endif #if defined(CONFIG_FSL_ESDHC) gd->arch.sdhc_clk = sdhc_clk; #endif @@ -491,7 +466,7 @@ int get_clocks(void) gd->arch.pciexp1_clk = pciexp1_clk; gd->arch.pciexp2_clk = pciexp2_clk; #endif -#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) gd->arch.sata_clk = sata_clk; #endif gd->pci_clk = pci_sync_in; @@ -559,10 +534,6 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc, printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->arch.i2c2_clk)); #endif -#if defined(CONFIG_ARCH_MPC8315) - printf(" TDM: %-4s MHz\n", - strmhz(buf, gd->arch.tdm_clk)); -#endif #if defined(CONFIG_FSL_ESDHC) printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->arch.sdhc_clk)); @@ -590,7 +561,7 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc, printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->arch.pciexp2_clk)); #endif -#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) printf(" SATA: %-4s MHz\n", strmhz(buf, gd->arch.sata_clk)); #endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 8a6896e622..b740675183 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -6,8 +6,7 @@ /* * The MCP83xx's 1-2 GPIO controllers each with 32 bits. */ -#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ - defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) #define MPC83XX_GPIO_CTRLRS 1 #elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) || \ defined(CONFIG_ARCH_MPC8309) diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 90bf5a2aea..2975255bfe 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -45,9 +45,6 @@ struct arch_global_data { # if defined(CONFIG_ARCH_MPC834X) u32 usbmph_clk; # endif /* CONFIG_ARCH_MPC834X */ -# if defined(CONFIG_ARCH_MPC8315) - u32 tdm_clk; -# endif u32 core_clk; u32 enc_clk; u32 lbiu_clk; @@ -57,7 +54,7 @@ struct arch_global_data { u32 pciexp1_clk; u32 pciexp2_clk; # endif -# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) +# if defined(CONFIG_ARCH_MPC837X) u32 sata_clk; # endif # if defined(CONFIG_ARCH_MPC8360) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index a03f938d9f..d2443dc90d 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -714,51 +714,6 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#elif defined(CONFIG_ARCH_MPC8315) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - gpio83xx_t gpio[1]; /* General purpose I/O module */ - u8 res0[0x1300]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[1]; /* I2C Controllers */ - u8 res1[0x1400]; - duart83xx_t duart[2]; /* DUART */ - u8 res2[0x900]; - fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ - u8 res3[0x1000]; - spi8xxx_t spi; /* Serial Peripheral Interface */ - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res4[0x80]; - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res5[0xa00]; - pex83xx_t pciexp[2]; /* PCI Express Controller */ - u8 res6[0xb000]; - tdm83xx_t tdm; /* TDM Controller */ - u8 res7[0x1e00]; - sata83xx_t sata[2]; /* SATA Controller */ - u8 res8[0x9000]; - usb83xx_t usb[1]; /* USB DR Controller */ - tsec83xx_t tsec[2]; - u8 res9[0x6000]; - tdmdmac83xx_t tdmdmac; /* TDM DMAC */ - u8 res10[0x2000]; - security83xx_t security; - u8 res11[0xA3000]; - serdes83xx_t serdes[1]; /* SerDes Registers */ - u8 res12[0x1CF00]; -} immap_t; - #elif defined(CONFIG_ARCH_MPC8308) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 470ee955f3..f2210a14ae 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -13,7 +13,6 @@ #if defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8309) || \ defined(CONFIG_ARCH_MPC8313) || \ - defined(CONFIG_ARCH_MPC8315) || \ defined(CONFIG_ARCH_MPC834X) || \ defined(CONFIG_ARCH_MPC837X) diff --git a/board/freescale/mpc8315erdb/Kconfig b/board/freescale/mpc8315erdb/Kconfig deleted file mode 100644 index f76b0d1d6d..0000000000 --- a/board/freescale/mpc8315erdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8315ERDB - -config SYS_BOARD - default "mpc8315erdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8315ERDB" - -endif diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS deleted file mode 100644 index cdac1ac2ee..0000000000 --- a/board/freescale/mpc8315erdb/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8315ERDB BOARD -#M: Dave Liu -S: Orphan (since 2018-05) -F: board/freescale/mpc8315erdb/ -F: include/configs/MPC8315ERDB.h -F: configs/MPC8315ERDB_defconfig -F: configs/MPC8315ERDB_NANDSPL_defconfig diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile deleted file mode 100644 index 579181999d..0000000000 --- a/board/freescale/mpc8315erdb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := mpc8315erdb.o sdram.o diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README deleted file mode 100644 index 8ad6d810c7..0000000000 --- a/board/freescale/mpc8315erdb/README +++ /dev/null @@ -1,105 +0,0 @@ -Freescale MPC8315ERDB Board ------------------------------------------ - -1. Board Switches and Jumpers - - S3 is used to set CONFIG_SYS_RESET_SOURCE. - - To boot the image at 0xFE000000 in NOR flash, use these DIP - switch settings for S3 S4: - - +------+ +------+ - | | | **** | - | **** | | | - +------+ ON +------+ ON - 4321 4321 - (where the '*' indicates the position of the tab of the switch.) - - To boot the image at the beginning of NAND flash, use these - DIP switch settings for S3 S4: - - +------+ +------+ - | * | | *** | - | *** | | * | - +------+ ON +------+ ON - 4321 4321 - (where the '*' indicates the position of the tab of the switch.) - - When booting from NAND, use u-boot-nand.bin, not u-boot.bin. - -2. Memory Map - The memory map looks like this: - - 0x0000_0000 0x07ff_ffff DDR 128M - 0x8000_0000 0x8fff_ffff PCI MEM 256M - 0x9000_0000 0x9fff_ffff PCI_MMIO 256M - 0xe000_0000 0xe00f_ffff IMMR 1M - 0xe030_0000 0xe03f_ffff PCI IO 1M - 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K - 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M - - When booting from NAND, NAND flash is CS0 and NOR flash - is CS1. - -3. Definitions - -3.1 Explanation of NEW definitions in: - - include/configs/MPC8315ERDB.h - - CONFIG_MPC83xx MPC83xx family - CONFIG_MPC831x MPC831x specific - CONFIG_MPC8315 MPC8315 specific - CONFIG_MPC8315ERDB MPC8315ERDB board specific - -4. Compilation - - Assuming you're using BASH (or similar) as your shell: - - export CROSS_COMPILE=your-cross-compiler-prefix- - make distclean - make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin) - make all - -5. Downloading and Flashing Images - -5.1 Reflash U-Boot Image using U-Boot - - NOR flash: - - tftp 40000 u-boot.bin - protect off all - erase fe000000 fe1fffff - - cp.b 40000 fe000000 xxxx - protect on all - - You have to supply the correct byte count with 'xxxx' - from the TFTP result log. - - NAND flash: - - =>tftpboot $loadaddr - =>nand erase 0 0x80000 - =>nand write $loadaddr 0 0x80000 - - ...where 0x80000 is the filesize rounded up to - the next 0x20000 increment. - -5.2 Downloading and Booting Linux Kernel - - Ensure that all networking-related environment variables are set - properly (including ipaddr, serverip, gatewayip (if needed), - netmask, ethaddr, eth1addr, rootpath (if using NFS root), - fdtfile, and bootfile). - - Then, do one of the following, depending on whether you - want an NFS root or a ramdisk root: - - =>run nfsboot - or - =>run ramboot - -6 Notes - - The console baudrate for MPC8315ERDB is 115200bps. diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c deleted file mode 100644 index e89d5d4955..0000000000 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Author: Scott Wood - * Dave Liu - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - gd->flags |= GD_FLG_SILENT; - - return 0; -} - -#ifndef CONFIG_NAND_SPL - -static u8 read_board_info(void) -{ - u8 val8; - i2c_set_bus_num(0); - - if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) - return val8; - else - return 0; -} - -int checkboard(void) -{ - static const char * const rev_str[] = { - "0.0", - "0.1", - "1.0", - "1.1", - "", - }; - u8 info; - int i; - - info = read_board_info(); - i = (!info) ? 4: info & 0x03; - - printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]); - - return 0; -} - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI_MEM_BASE, - phys_start: CONFIG_SYS_PCI_MEM_PHYS, - size: CONFIG_SYS_PCI_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI_MMIO_BASE, - phys_start: CONFIG_SYS_PCI_MMIO_PHYS, - size: CONFIG_SYS_PCI_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI_IO_BASE, - phys_start: CONFIG_SYS_PCI_IO_PHYS, - size: CONFIG_SYS_PCI_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static struct pci_region pcie_regions_1[] = { - { - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, - .size = CONFIG_SYS_PCIE2_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE2_IO_BASE, - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, - .size = CONFIG_SYS_PCIE2_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile sysconf83xx_t *sysconf = &immr->sysconf; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *reg[] = { pci_regions }; - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - - /* Enable all 3 PCI_CLK_OUTPUTs. */ - clk->occr |= 0xe0000000; - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); - - /* Configure the clock for PCIE controller */ - clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, - SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - out_be32(&sysconf->pecr2, 0xE0008000); - udelay(2000); - - /* Configure PCI Express Local Access Windows */ - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(2, pcie_reg); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void fdt_tsec1_fixup(void *fdt, struct bd_info *bd) -{ - const char disabled[] = "disabled"; - const char *path; - int ret; - - if (hwconfig_arg_cmp("board_type", "tsec1")) { - return; - } else if (!hwconfig_arg_cmp("board_type", "ulpi")) { - printf("NOTICE: No or unknown board_type hwconfig specified.\n" - " Assuming board with TSEC1.\n"); - return; - } - - ret = fdt_path_offset(fdt, "/aliases"); - if (ret < 0) { - printf("WARNING: can't find /aliases node\n"); - return; - } - - path = fdt_getprop(fdt, ret, "ethernet0", NULL); - if (!path) { - printf("WARNING: can't find ethernet0 alias\n"); - return; - } - - do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_tsec1_fixup(blob, bd); - - return 0; -} -#endif - -int board_eth_init(struct bd_info *bis) -{ - cpu_eth_init(bis); /* Initialize TSECs first */ - return pci_eth_init(bis); -} - -#else /* CONFIG_NAND_SPL */ - -int checkboard(void) -{ - puts("Board: Freescale MPC8315ERDB\n"); - return 0; -} - -void board_init_f(ulong bootflag) -{ - board_early_init_f(); - ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - puts("NAND boot... "); - timer_init(); - dram_init(); - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, - CONFIG_SYS_NAND_U_BOOT_RELOC); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (gd->flags & GD_FLG_SILENT) - return; - - if (c == '\n') - ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r'); - - ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c); -} - -#endif /* CONFIG_NAND_SPL */ diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c deleted file mode 100644 index ffbb79aaec..0000000000 --- a/board/freescale/mpc8315erdb/sdram.c +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Authors: Nick.Spence@freescale.com - * Wilson.Lo@freescale.com - * scottwood@freescale.com - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void resume_from_sleep(void) -{ - u32 magic = *(u32 *)0; - - typedef void (*func_t)(void); - func_t resume = *(func_t *)4; - - if (magic == 0xf5153ae5) - resume(); - - gd->flags &= ~GD_FLG_SILENT; - puts("\nResume from sleep failed: bad magic word\n"); -} - -/* Fixed sdram init -- doesn't use serial presence detect. - * - * This is useful for faster booting in configs where the RAM is unlikely - * to be changed, or for things like NAND booting where space is tight. - */ -#ifndef CONFIG_SYS_RAMBOOT -static long fixed_sdram(void) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; - u32 msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; - - /* - * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], - * or the DDR2 controller may fail to initialize correctly. - */ - __udelay(50000); - - im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - - /* Currently we use only one CS, so disable the other bank. */ - im->ddr.cs_config[1] = 0; - - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI; - else - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - sync(); - - /* enable DDR controller */ - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - sync(); - - return msize; -} -#else -static long fixed_sdram(void) -{ - return CONFIG_SYS_DDR_SIZE * 1024 * 1024; -} -#endif /* CONFIG_SYS_RAMBOOT */ - -int dram_init(void) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - u32 msize; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -ENXIO; - - /* DDR SDRAM */ - msize = fixed_sdram(); - - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - resume_from_sleep(); - - /* set total bus SDRAM size(bytes) -- DDR */ - gd->ram_size = msize; - - return 0; -} diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig deleted file mode 100644 index fa22196526..0000000000 --- a/configs/MPC8315ERDB_defconfig +++ /dev/null @@ -1,156 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_CLK_FREQ=66666667 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC8315ERDB=y -CONFIG_SYSTEM_PLL_VCO_DIV_2=y -CONFIG_CORE_PLL_RATIO_3_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_RGMII=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_128_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="IMMRBAR" -CONFIG_BAT1_BASE=0xE0000000 -CONFIG_BAT1_LENGTH_8_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y -CONFIG_BAT1_DCACHE_INHIBITED=y -CONFIG_BAT1_DCACHE_GUARDED=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="FLASH" -CONFIG_BAT2_BASE=0xFE000000 -CONFIG_BAT2_LENGTH_32_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="STACK_IN_DCACHE" -CONFIG_BAT3_BASE=0xE6000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_BAT4=y -CONFIG_BAT4_NAME="PCI_MEM_PHYS" -CONFIG_BAT4_BASE=0x80000000 -CONFIG_BAT4_LENGTH_256_MBYTES=y -CONFIG_BAT4_ACCESS_RW=y -CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT4_USER_MODE_VALID=y -CONFIG_BAT4_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="PCI_MMIO_PHYS" -CONFIG_BAT5_BASE=0x90000000 -CONFIG_BAT5_LENGTH_256_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_8_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE0600000 -CONFIG_LBLAW1_NAME="NAND" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_8_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="NAND" -CONFIG_BR1_OR1_BASE=0xE0600000 -CONFIG_BR1_ERRORCHECKING_BOTH=y -CONFIG_BR1_MACHINE_FCM=y -CONFIG_OR1_SCY_1=y -CONFIG_OR1_CSCT_8_CYCLE=y -CONFIG_OR1_CST_ONE_CLOCK=y -CONFIG_OR1_CHT_TWO_CLOCK=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_DPM=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_CMD_PCI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=e0600000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_ADDR=0xFE080000 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_EEPRO100=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h deleted file mode 100644 index 688aa5ea98..0000000000 --- a/include/configs/MPC8315ERDB.h +++ /dev/null @@ -1,370 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. - * - * Dave Liu - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ - -#define CONFIG_HWCONFIG - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of two chips HY5PS12621BFP-C4 from HYNIX - */ -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (6 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x27256222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x121048c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03600100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32) - /* 0x43080000 */ -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0232 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -/* 127 64KB sectors and 8 8KB top sectors per device */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * NAND Flash on the Local Bus - */ - -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xFFF00000 -#else -#define CONFIG_SYS_NAND_BASE 0xE0600000 -#endif - -#define CONFIG_MTD_PARTITION - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 -#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 - - - -/* Still needed for spl_minimal.c */ -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM - -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ - !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * Board info - revision and where boot from - */ -#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_SYS_SCCR_USBDRCM 3 - -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_PHY_TYPE "utmi" -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC1" - -/* - * SATA - */ -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * MMU Setup - */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc8315erdb.dtb\0" \ - "usb_phy_type=utmi\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index ea67868ea0..71cffa1b0f 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -243,41 +243,6 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001 -#elif defined(CONFIG_ARCH_MPC8315) -/* SICRL bits - MPC8315 specific */ -#define SICRL_DMA_CH0 0xc0000000 -#define SICRL_DMA_SPI 0x30000000 -#define SICRL_UART 0x0c000000 -#define SICRL_IRQ4 0x02000000 -#define SICRL_IRQ5 0x01800000 -#define SICRL_IRQ6_7 0x00400000 -#define SICRL_IIC1 0x00300000 -#define SICRL_TDM 0x000c0000 -#define SICRL_TDM_SHARED 0x00030000 -#define SICRL_PCI_A 0x0000c000 -#define SICRL_ELBC_A 0x00003000 -#define SICRL_ETSEC1_A 0x000000c0 -#define SICRL_ETSEC1_B 0x00000030 -#define SICRL_ETSEC1_C 0x0000000c -#define SICRL_TSEXPOBI 0x00000001 - -/* SICRH bits - MPC8315 specific */ -#define SICRH_GPIO_0 0xc0000000 -#define SICRH_GPIO_1 0x30000000 -#define SICRH_GPIO_2 0x0c000000 -#define SICRH_GPIO_3 0x03000000 -#define SICRH_GPIO_4 0x00c00000 -#define SICRH_GPIO_5 0x00300000 -#define SICRH_GPIO_6 0x000c0000 -#define SICRH_GPIO_7 0x00030000 -#define SICRH_GPIO_8 0x0000c000 -#define SICRH_GPIO_9 0x00003000 -#define SICRH_GPIO_10 0x00000c00 -#define SICRH_GPIO_11 0x00000300 -#define SICRH_ETSEC2_A 0x000000c0 -#define SICRH_TSOBI1 0x00000002 -#define SICRH_TSOBI2 0x00000001 - #elif defined(CONFIG_ARCH_MPC837X) /* SICRL bits - MPC837X specific */ #define SICRL_USB_A 0xC0000000 @@ -634,7 +599,7 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_2 0x00000000 @@ -981,7 +946,7 @@ #define SCCR_USBDRCM_2 0x00200000 #define SCCR_USBDRCM_3 0x00300000 -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) /* SCCR bits - MPC8315/MPC8308 specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 -- 2.39.5