controller register space
- Serial Ports:
- CONFIG_PL010_SERIAL
-
- Define this if you want support for Amba PrimeCell PL010 UARTs.
-
CONFIG_PL011_SERIAL
Define this if you want support for Amba PrimeCell PL011 UARTs.
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL
-config TARGET_EDB93XX
- bool "Support edb93xx"
- select CPU_ARM920T
- select GPIO_EXTRA_HEADER
- select PL010_SERIAL
-
config TARGET_ASPENITE
bool "Support aspenite"
select CPU_ARM926EJS
source "board/broadcom/bcm968580xref/Kconfig"
source "board/broadcom/bcmns3/Kconfig"
source "board/cavium/thunderx/Kconfig"
-source "board/cirrus/edb93xx/Kconfig"
source "board/eets/pdu001/Kconfig"
source "board/emulation/qemu-arm/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
+++ /dev/null
-if TARGET_EDB93XX
-
-config SYS_BOARD
- default "edb93xx"
-
-config SYS_VENDOR
- default "cirrus"
-
-config SYS_SOC
- default "ep93xx"
-
-config SYS_CONFIG_NAME
- default "edb93xx"
-
-endif
+++ /dev/null
-EDB93XX BOARD
-M: Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
-S: Maintained
-F: board/cirrus/edb93xx/
-F: include/configs/edb93xx.h
-F: configs/edb9315a_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2013
-# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
-#
-
-obj-y := edb93xx.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Board initialization for EP93xx
- *
- * Copyright (C) 2013
- * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
- *
- * Copyright (C) 2009
- * Matthias Kaehlcke <matthias <at> kaehlcke.net>
- *
- * (C) Copyright 2002 2003
- * Network Audio Technologies, Inc. <www.netaudiotech.com>
- * Adam Bezanson <bezanson <at> netaudiotech.com>
- */
-
-#include <config.h>
-#include <common.h>
-#include <cpu_func.h>
-#include <init.h>
-#include <irq_func.h>
-#include <net.h>
-#include <netdev.h>
-#include <status_led.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/arch/ep93xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * usb_div: 4, nbyp2: 1, pll2_en: 1
- * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
- * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
- */
-#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
- 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
- 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
- 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
- SYSCON_CLKSET2_PLL2_EN | \
- SYSCON_CLKSET2_NBYP2 | \
- 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
-
-#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
- SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
- 1 << SMC_BCR_MW_SHIFT)
-
-/* delay execution before timers are initialized */
-static inline void early_udelay(uint32_t usecs)
-{
- /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
- register uint32_t loops = (usecs * 1000) / 20;
-
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b" : "=r" (loops) : "0" (loops));
-}
-
-#ifndef CONFIG_EP93XX_NO_FLASH_CFG
-static void flash_cfg(void)
-{
- struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
-
- writel(SMC_BCR6_VALUE, &smc->bcr6);
-}
-#else
-#define flash_cfg()
-#endif
-
-int board_init(void)
-{
- /*
- * Setup PLL2, PPL1 has been set during lowlevel init
- */
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- writel(CLKSET2_VAL, &syscon->clkset2);
-
- /*
- * the user's guide recommends to wait at least 1 ms for PLL2 to
- * stabilize
- */
- early_udelay(1000);
-
- /* Go to Async mode */
- __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
- __asm__ volatile ("orr r0, r0, #0xc0000000");
- __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
-
- icache_enable();
-
-#ifdef USE_920T_MMU
- dcache_enable();
-#endif
-
- /* Machine number, as defined in linux/arch/arm/tools/mach-types */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- /* We have a console */
- gd->have_console = 1;
-
- enable_interrupts();
-
- flash_cfg();
-
- green_led_on();
- red_led_off();
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /*
- * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
- * 14.7456/2 MHz
- */
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
- return 0;
-}
-
-int board_eth_init(struct bd_info *bd)
-{
- return ep93xx_eth_initialize(0, MAC_BASE);
-}
-
-static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
- unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
-{
- if (dram_bank_cnt == 1) {
- dram_bank_base[0] = PHYS_SDRAM_1;
- } else {
- /* Table lookup for holes in address space. Maximum memory
- * for the single SDCS may be up to 256Mb. We start scanning
- * banks from 1Mb, so it could be up to 128 banks theoretically.
- * We need at maximum 7 bits for the loockup, 8 slots is
- * enough for the worst case.
- */
- unsigned tbl[8];
- unsigned i = dram_bank_cnt / 2;
- unsigned j = 0x00100000; /* 1 Mb */
- unsigned *ptbl = tbl;
- do {
- while (!(dram_addr_mask & j)) {
- j <<= 1;
- }
- *ptbl++ = j;
- j <<= 1;
- i >>= 1;
- } while (i != 0);
-
- for (i = dram_bank_cnt, j = 0;
- (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
- unsigned addr = PHYS_SDRAM_1;
- unsigned k;
- unsigned bit;
-
- for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
- if (bit & j)
- addr |= tbl[k];
- }
-
- dram_bank_base[j] = addr;
- }
- }
-}
-
-/* called in board_init_f (before relocation) */
-static unsigned dram_init_banksize_int(int print)
-{
- /*
- * Collect information of banks that has been filled during lowlevel
- * initialization
- */
- unsigned i;
- unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
- unsigned dram_total = 0;
- unsigned dram_bank_size = *(unsigned *)
- (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
- unsigned dram_addr_mask = *(unsigned *)
- (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
- unsigned dram_bank_cnt = *(unsigned *)
- (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
-
- dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
-
- for (i = 0; i < dram_bank_cnt; i++) {
- gd->bd->bi_dram[i].start = dram_bank_base[i];
- gd->bd->bi_dram[i].size = dram_bank_size;
- dram_total += dram_bank_size;
- }
- for (; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = 0;
- gd->bd->bi_dram[i].size = 0;
- }
-
- if (print) {
- printf("DRAM mask: %08x\n", dram_addr_mask);
- printf("DRAM total %u banks:\n", dram_bank_cnt);
- printf("bank base-address size\n");
-
- if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
- printf("WARNING! UBoot was configured for %u banks,\n"
- "but %u has been found. "
- "Supressing extra memory banks\n",
- CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
- dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
- }
-
- for (i = 0; i < dram_bank_cnt; i++) {
- printf(" %u %08x %08x\n",
- i, dram_bank_base[i], dram_bank_size);
- }
- printf(" ------------------------------------------\n"
- "Total %9d\n\n",
- dram_total);
- }
-
- return dram_total;
-}
-
-int dram_init_banksize(void)
-{
- dram_init_banksize_int(0);
-
- return 0;
-}
-
-/* called in board_init_f (before relocation) */
-int dram_init(void)
-{
- struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
- unsigned sec_id = readl(SECURITY_EXTENSIONID);
- unsigned chip_id = readl(&syscon->chipid);
-
- printf("CPU: Cirrus Logic ");
- switch (sec_id & 0x000001FE) {
- case 0x00000008:
- printf("EP9301");
- break;
- case 0x00000004:
- printf("EP9307");
- break;
- case 0x00000002:
- printf("EP931x");
- break;
- case 0x00000000:
- printf("EP9315");
- break;
- default:
- printf("<unknown>");
- break;
- }
-
- printf(" - Rev. ");
- switch (chip_id & 0xF0000000) {
- case 0x00000000:
- printf("A");
- break;
- case 0x10000000:
- printf("B");
- break;
- case 0x20000000:
- printf("C");
- break;
- case 0x30000000:
- printf("D0");
- break;
- case 0x40000000:
- printf("D1");
- break;
- case 0x50000000:
- printf("E0");
- break;
- case 0x60000000:
- printf("E1");
- break;
- case 0x70000000:
- printf("E2");
- break;
- default:
- printf("?");
- break;
- }
- printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
-
- gd->ram_size = dram_init_banksize_int(1);
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * Copyright (C) 2013
- * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
- *
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text : {
- *(.__image_copy_start)
- *(.vectors)
- arch/arm/cpu/arm920t/start.o (.text*)
- . = 0x1000;
-
- LONG(0x53555243)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- /*
- * Deprecated: this MMU section is used by pxa at present but
- * should not be used by new boards/CPUs.
- */
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu.hash : { *(.gnu.hash) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
- .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
-}
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_EDB93XX=y
-CONFIG_SYS_TEXT_BASE=0x60000000
-CONFIG_NR_DRAM_BANKS=8
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="EDB9315A> "
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-# CONFIG_DOS_PARTITION is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0x60040000
-CONFIG_ENV_ADDR_REDUND=0x60060000
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=0
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS1=y
-CONFIG_LED_STATUS_BIT1=1
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
-CONFIG_LED_STATUS_RED_ENABLE=y
-CONFIG_LED_STATUS_RED=1
-CONFIG_LED_STATUS_GREEN_ENABLE=y
-CONFIG_LED_STATUS_GREEN=0
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MII=y
-CONFIG_CONS_INDEX=0
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
config DEBUG_UART_PL010
bool "pl010"
- depends on PL01X_SERIAL || PL010_SERIAL
+ depends on PL01X_SERIAL
help
Select this to enable a debug UART using the pl01x driver with the
PL010 UART type. You will need to provide parameters to make this
Select this to enable a UART for Intel MID platforms.
This uses the ns16550 driver as a library.
-config PL010_SERIAL
- bool "ARM PL010 driver"
- depends on !DM_SERIAL
- help
- Select this to enable a UART for platforms using PL010.
-
config PL011_SERIAL
bool "ARM PL011 driver"
depends on !DM_SERIAL
ifdef CONFIG_DM_SERIAL
obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
else
-obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
endif
{
int clock = 0;
-#if defined(CONFIG_PL010_SERIAL)
- pl01x_type = TYPE_PL010;
-#elif defined(CONFIG_PL011_SERIAL)
+#if defined(CONFIG_PL011_SERIAL)
pl01x_type = TYPE_PL011;
clock = CONFIG_PL011_CLOCK;
#endif
+++ /dev/null
-/*
- * U-Boot - Configuration file for Cirrus Logic EDB93xx boards
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_MK_edb9301
-#define CONFIG_EDB9301
-#elif defined(CONFIG_MK_edb9302)
-#define CONFIG_EDB9302
-#elif defined(CONFIG_MK_edb9302a)
-#define CONFIG_EDB9302A
-#elif defined(CONFIG_MK_edb9307)
-#define CONFIG_EDB9307
-#elif defined(CONFIG_MK_edb9307a)
-#define CONFIG_EDB9307A
-#elif defined(CONFIG_MK_edb9312)
-#define CONFIG_EDB9312
-#elif defined(CONFIG_MK_edb9315)
-#define CONFIG_EDB9315
-#elif defined(CONFIG_MK_edb9315a)
-#define CONFIG_EDB9315A
-#else
-#error "no board defined"
-#endif
-
-/* Initial environment and monitor configuration options. */
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_BOOTFILE "edb93xx.img"
-
-#ifdef CONFIG_EDB9301
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301
-#elif defined(CONFIG_EDB9302)
-#define CONFIG_EP9302
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302
-#elif defined(CONFIG_EDB9302A)
-#define CONFIG_EP9302
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A
-#elif defined(CONFIG_EDB9307)
-#define CONFIG_EP9307
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307
-#elif defined(CONFIG_EDB9307A)
-#define CONFIG_EP9307
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A
-#elif defined(CONFIG_EDB9312)
-#define CONFIG_EP9312
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312
-#elif defined(CONFIG_EDB9315)
-#define CONFIG_EP9315
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315
-#elif defined(CONFIG_EDB9315A)
-#define CONFIG_EP9315
-#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A
-#else
-#error "no board defined"
-#endif
-
-/* High-level configuration options */
-#define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */
-
-#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
-
-/* Monitor configuration */
-
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
-
-/* Serial port hardware configuration */
-#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \
- 115200, 230400}
-#define CONFIG_SYS_SERIAL0 0x808C0000
-#define CONFIG_SYS_SERIAL1 0x808D0000
-/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1} */
-
-#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
-
-/* Status LED */
-/* Optional value */
-
-/* Network hardware configuration */
-#define CONFIG_DRIVER_EP93XX_MAC
-#define CONFIG_MII_SUPPRESS_PREAMBLE
-
-/* SDRAM configuration */
-#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
- defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
- defined(CONFIG_EDB9315)
-/*
- * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
- * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
- * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
- *
- * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
- * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
- * 64 MB of SDRAM.
- */
-
-#define CONFIG_EDB93XX_SDCS3
-
-#elif defined(CONFIG_EDB9302A) || \
- defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
-/*
- * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
- * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
- * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
- *
- * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
- * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
- */
-#define CONFIG_EDB93XX_SDCS0
-
-#else
-#error "no SDCS configuration for this board"
-#endif
-
-#if defined(CONFIG_EDB93XX_SDCS3)
-#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
-#define PHYS_SDRAM_1 0x00000000
-#elif defined(CONFIG_EDB93XX_SDCS0)
-#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
-#define PHYS_SDRAM_1 0xc0000000
-#endif
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)
-
-/* Must match kernel config */
-#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
-
-/* Run-time memory allocatons */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-
-/* -----------------------------------------------------------------------------
- * FLASH and environment organization
- *
- * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at
- * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit
- * data bus, for a total of 16 MB of CFI-compatible flash.
- *
- * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at
- * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
- * data bus, for a total of 32 MB of CFI-compatible flash.
- *
- *
- * EDB9301/02(a)7a/15a EDB9307/12/15
- * 0x60000000 - 0x0003FFFF u-boot u-boot
- * 0x60040000 - 0x0005FFFF environment #1 environment #1
- * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued)
- * 0x60080000 - 0x0009FFFF unused environment #2
- * 0x600A0000 - 0x000BFFFF unused environment #2 (continued)
- * 0x600C0000 - 0x00FFFFFF unused unused
- * 0x61000000 - 0x01FFFFFF not present unused
- */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT (256+8)
-
-#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_OHCI_EP93XX
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci"
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000
-
-/* Define to disable flash configuration*/
-/* #define CONFIG_EP93XX_NO_FLASH_CFG */
-
-/* Define this for indusrial rated chips */
-/* #define CONFIG_EDB93XX_INDUSTRIAL */
-
-#endif /* !defined (__CONFIG_H) */
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