From: Shiraz Hashim <shiraz.hashim@st.com>
Date: Mon, 7 May 2012 07:37:00 +0000 (+0530)
Subject: SPEAr: Correct SoC ID offset in misc configuration space
X-Git-Tag: v2025.01-rc5-pxa1908~17673^2~35^2~24^2~19
X-Git-Url: http://git.dujemihanovic.xyz/projects?a=commitdiff_plain;h=f28e5c946d6c88b1c8639896863c7ad7d8889bf4;p=u-boot.git

SPEAr: Correct SoC ID offset in misc configuration space

SoC Core ID offset is 0x30 in miscellaneous configuration address
space. It was wrongly mentioned as periph2 clk enable.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---

diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
index 384944d33e..b8fcf49feb 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -37,7 +37,7 @@ struct misc_regs {
 	u32 amba_clk_cfg;	/* 0x24 */
 	u32 periph_clk_cfg;	/* 0x28 */
 	u32 periph1_clken;	/* 0x2C */
-	u32 periph2_clken;	/* 0x30 */
+	u32 soc_core_id;	/* 0x30 */
 	u32 ras_clken;		/* 0x34 */
 	u32 periph1_rst;	/* 0x38 */
 	u32 periph2_rst;	/* 0x3C */