From: Chanho Park Date: Sun, 5 Nov 2023 23:13:15 +0000 (+0900) Subject: clk: starfive: jh7110: Add watchdog clocks X-Git-Url: http://git.dujemihanovic.xyz/projects?a=commitdiff_plain;h=8ef2d7926f6973707164f4bd8f76bb94e80f336b;p=u-boot.git clk: starfive: jh7110: Add watchdog clocks Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110 watchdog device. Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index a835541e48..a38694809a 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev) starfive_clk_gate(priv->reg, "i2c5_apb", "apb0", OFFSET(JH7110_SYSCLK_I2C5_APB))); + /* Watchdog clocks */ + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB), + starfive_clk_gate(priv->reg, + "wdt_apb", "apb0", + OFFSET(JH7110_SYSCLK_WDT_APB))); + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE), + starfive_clk_gate(priv->reg, + "wdt_core", "oscillator", + OFFSET(JH7110_SYSCLK_WDT_CORE))); /* enable noc_bus_stg_axi clock */ if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))