/*
* DDR3 init / training code ported from Marvell bin_hdr. Now
* available in mainline U-Boot in:
- * drivers/ddr/mvebu/
+ * drivers/ddr/marvell
*/
int ddr3_init(void);
#endif /* __ASSEMBLY__ */
#ifndef __HIGHSPEED_ENV_SPEC_H
#define __HIGHSPEED_ENV_SPEC_H
-#include "../../../drivers/ddr/mvebu/ddr3_hw_training.h"
+#include "../../../drivers/ddr/marvell/axp/ddr3_hw_training.h"
typedef enum {
SERDES_UNIT_UNCONNECTED = 0x0,
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR
+#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_SPD_EEPROM 0x4e
#endif /* _CONFIG_DB_MV7846MP_GP_H */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR
+#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
#endif /* _CONFIG_DB_MV7846MP_GP_H */
libs-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/
libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/
libs-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/
-libs-$(CONFIG_SYS_MVEBU_DDR) += drivers/ddr/mvebu/
+libs-$(CONFIG_SYS_MVEBU_DDR_AXP) += drivers/ddr/marvell/axp/
libs-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/
libs-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/
libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/