clk: mediatek: mt7622: fix broken peri_cgs clk with XTAL parents

Fix broken peri_cgs clock with XTAL parents as they have wrong
definition of the parent type.

Correctly fix them and use CLK_PARENT_XTAL for them.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 2beb63030f22a4e620ddc2816c5cb57f2f275132..4a7c5faff1a6cc33268e5b2872949deb3e45f615 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -402,13 +402,17 @@ static const struct mtk_gate_regs peri1_cg_regs = {
        .sta_ofs = 0x1C,
 };
 
-#define GATE_PERI0(_id, _parent, _shift) {                     \
+#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) {       \
                .id = _id,                                      \
                .parent = _parent,                              \
                .regs = &peri0_cg_regs,                         \
                .shift = _shift,                                \
-               .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+               .flags = _flags,                                \
        }
+#define GATE_PERI0(_id, _parent, _shift) \
+       GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_PERI0_XTAL(_id, _parent, _shift) \
+       GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
 
 #define GATE_PERI1(_id, _parent, _shift) {                     \
                .id = _id,                                      \
@@ -421,14 +425,14 @@ static const struct mtk_gate_regs peri1_cg_regs = {
 static const struct mtk_gate peri_cgs[] = {
        /* PERI0 */
        GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
-       GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
-       GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
-       GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
-       GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
-       GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
-       GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
-       GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
-       GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9),
+       GATE_PERI0_XTAL(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
+       GATE_PERI0_XTAL(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
+       GATE_PERI0_XTAL(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
+       GATE_PERI0_XTAL(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
+       GATE_PERI0_XTAL(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
+       GATE_PERI0_XTAL(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
+       GATE_PERI0_XTAL(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
+       GATE_PERI0_XTAL(CLK_PERI_PWM_PD, CLK_XTAL, 9),
        GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
        GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
        GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
@@ -441,7 +445,7 @@ static const struct mtk_gate peri_cgs[] = {
        GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
        GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
        GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
-       GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
+       GATE_PERI0_XTAL(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
        GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
        GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29),
        GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),