ARM: am335x: Add phyBOARD REGOR support

phyBOARD-REGOR is based on phyCORE AM335x R2 SoM (PCL060).

CPU  : AM335X-GP rev 2.1
Model: Phytec AM335x phyBOARD-REGOR
DRAM:  512 MiB
NAND:  512 MiB
MMC:   OMAP SD/MMC: 0
eth0: ethernet@4a100000

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART
 - USB (host)

Device trees were taken from Linux mainline:
commit c4d6fe731176 ("Linux 5.9.0")

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5308713df7d08c20c857f4ac3f80cebd30739980..43192073bf7cd9ca977b5e08f4dafb33c1994778 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -350,7 +350,8 @@ dtb-$(CONFIG_AM33XX) += \
        am335x-sl50.dtb \
        am335x-base0033.dtb \
        am335x-guardian.dtb \
-       am335x-wega-rdk.dtb
+       am335x-wega-rdk.dtb \
+       am335x-regor-rdk.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb    \
        am43x-epos-evm.dtb \
        am437x-idk-evm.dtb \

diff --git a/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
new file mode 100644 (file)
index 0000000..1ddd715
--- /dev/null
+++ b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Linumiz
+ */
+
+/ {
+       chosen {
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               bootargs = "console=ttyO0,115200 earlyprintk";
+               stdout-path = &uart0;
+       };
+
+       ocp {
+               u-boot,dm-pre-reloc;
+       };
+};
+
+&i2c0 {
+       u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+       u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+       u-boot,dm-pre-reloc;
+       cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};

diff --git a/arch/arm/dts/am335x-regor-rdk.dts b/arch/arm/dts/am335x-regor-rdk.dts
new file mode 100644 (file)
index 0000000..66a1360
--- /dev/null
+++ b/arch/arm/dts/am335x-regor-rdk.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "am335x-phycore-som.dtsi"
+#include "am335x-regor.dtsi"
+
+/* SoM */
+&gpmc {
+       status = "okay";
+};
+
+&i2c_eeprom {
+       status = "okay";
+};
+
+&serial_flash {
+       status = "okay";
+};

diff --git a/arch/arm/dts/am335x-regor.dtsi b/arch/arm/dts/am335x-regor.dtsi
new file mode 100644 (file)
index 0000000..86b3f07
--- /dev/null
+++ b/arch/arm/dts/am335x-regor.dtsi
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ */
+
+/ {
+       model = "Phytec AM335x phyBOARD-REGOR";
+       compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx";
+
+       vcc3v3: fixedregulator@1 {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc3v3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+       };
+
+       /* User IO */
+       user_leds: user_leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&user_leds_pins>;
+
+               run_stop-led {
+                       gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "gpio";
+                       default-state = "off";
+               };
+
+               error-led {
+                       gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "gpio";
+                       default-state = "off";
+               };
+       };
+};
+
+/* User Leds */
+&am33xx_pinmux {
+       user_leds_pins: pinmux_user_leds {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* lcd_hsync.gpio2_22 */
+                       AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* mcasp0_fsx.gpio3_15 */
+               >;
+       };
+};
+
+/* CAN Busses */
+&am33xx_pinmux {
+       dcan1_pins: pinmux_dcan1 {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2)      /* uart0_ctsn.d_can1_tx */
+                       AM33XX_IOPAD(0x96C, PIN_INPUT_PULLUP | MUX_MODE2)       /* uart0_rtsn.d_can1_rx */
+               >;
+       };
+};
+
+&dcan1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&dcan1_pins>;
+       status = "okay";
+};
+
+/* Ethernet */
+&am33xx_pinmux {
+       ethernet1_pins: pinmux_ethernet1 {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a0.mii2_txen */
+                       AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a1.mii2_rxdv */
+                       AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a2.mii2_txd3 */
+                       AM33XX_IOPAD(0x84C, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a3.mii2_txd2 */
+                       AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a4.mii2_txd1 */
+                       AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)             /* gpmc_a5.mii2_txd0 */
+                       AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a6.mii2_txclk */
+                       AM33XX_IOPAD(0x85C, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a7.mii2_rxclk */
+                       AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a8.mii2_rxd3 */
+                       AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)      /* gpmc_a9.mii2_rxd2 */
+                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a10.mii2_rxd1 */
+                       AM33XX_IOPAD(0x86C, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_a11.mii2_rxd0 */
+                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_wpn.mii2_rxerr */
+                       AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* gpmc_ben1.mii2_col */
+               >;
+       };
+};
+
+&cpsw_emac1 {
+       phy-handle = <&phy1>;
+       phy-mode = "mii";
+       dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+       };
+};
+
+&mac {
+       slaves = <2>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
+       dual_emac = <1>;
+};
+
+/* GPIOs */
+&am33xx_pinmux {
+       pinctrl-names = "default";
+       pinctrl-0 = <&user_gpios_pins>;
+
+       user_gpios_pins: pinmux_user_gpios {
+               pinctrl-single,pins = <
+                       /* DIGIN 1-4 */
+                       AM33XX_IOPAD(0x82C, PIN_INPUT | MUX_MODE7)              /* gpmc_ad11.gpio0_27 */
+                       AM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE7)              /* gpmc_ad10.gpio0_26 */
+                       AM33XX_IOPAD(0x824, PIN_INPUT | MUX_MODE7)              /* gpmc_ad9.gpio0_23 */
+                       AM33XX_IOPAD(0x820, PIN_INPUT | MUX_MODE7)              /* gpmc_ad8.gpio0_22 */
+                       /* DIGOUT 1-4 */
+                       AM33XX_IOPAD(0x83C, PIN_OUTPUT | MUX_MODE7)             /* gpmc_ad15.gpio1_15 */
+                       AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE7)             /* gpmc_ad14.gpio1_14 */
+                       AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE7)             /* gpmc_ad13.gpio1_13 */
+                       AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE7)             /* gpmc_ad12.gpio1_12 */
+               >;
+       };
+};
+
+/* MMC */
+&am33xx_pinmux {
+       mmc1_pins: pinmux_mmc1 {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x8F0, PIN_INPUT_PULLUP | MUX_MODE0)
+                       AM33XX_IOPAD(0x8F4, PIN_INPUT_PULLUP | MUX_MODE0)
+                       AM33XX_IOPAD(0x8F8, PIN_INPUT_PULLUP | MUX_MODE0)
+                       AM33XX_IOPAD(0x8FC, PIN_INPUT_PULLUP | MUX_MODE0)
+                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
+                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
+                       AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)       /* spi0_cs1.mmc0_sdcd */
+               >;
+       };
+};
+
+&mmc1 {
+       vmmc-supply = <&vcc3v3>;
+       bus-width = <4>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc1_pins>;
+       cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+/* RTC */
+&i2c_rtc {
+       status = "okay";
+};
+
+/* UARTs */
+&am33xx_pinmux {
+       uart0_pins: pinmux_uart0 {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
+                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+               >;
+       };
+
+       uart2_pins: pinmux_uart2 {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x92C, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_tx_clk.uart2_rxd */
+                       AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_rx_clk.uart2_txd */
+               >;
+       };
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart2_pins>;
+       status = "okay";
+};
+
+/* RS485 - UART1 */
+&am33xx_pinmux {
+       uart1_rs485_pins: pinmux_uart1_rs485_pins {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)
+                       AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+                       AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLUP | MUX_MODE0)
+               >;
+       };
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart1_rs485_pins>;
+       status = "okay";
+       linux,rs485-enabled-at-boot-time;
+};

diff --git a/board/phytec/phycore_am335x_r2/MAINTAINERS b/board/phytec/phycore_am335x_r2/MAINTAINERS
index e56f30fdc09f6dc1630c3360696bf634b69fa471..8d02b0e19801e77f4dcfb79722cc9e8589671b5b 100644 (file)
--- a/board/phytec/phycore_am335x_r2/MAINTAINERS
+++ b/board/phytec/phycore_am335x_r2/MAINTAINERS
@@ -1,7 +1,11 @@
 phyCORE AM335x R2 WEGA BOARD
 M:     Niel Fourie <lusus@denx.de>
-M:     Parthiban Nallathambi <pn@denx.de>
+M:     Parthiban Nallathambi <parthiban@linumiz.com>
 S:     Maintained
+F:     arch/arm/dts/am335x-regor.dtsi
+F:     arch/arm/dts/am335x-regor-rdk.dts
+F:     arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
 F:     board/phytec/phycore_am335x_r2
 F:     include/configs/phycore_am335x_r2.h
+F:     configs/phycore-am335x-r2-regor_defconfig
 F:     configs/phycore-am335x-r2-wega_defconfig

diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig
new file mode 100644 (file)
index 0000000..6d40497
--- /dev/null
+++ b/configs/phycore-am335x-r2-regor_defconfig
@@ -0,0 +1,88 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_OFFSET=0xA0000
+CONFIG_AM33XX=y
+CONFIG_SYS_MPUCLK=1000
+CONFIG_TARGET_PHYCORE_AM335X_R2=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_DEFAULT_DEVICE_TREE="am335x-regor-rdk"
+# CONFIG_FIT is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="am335x-regor-rdk.dtb"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NAND_DRIVERS=y
+CONFIG_SPL_NAND_ECC=y
+CONFIG_SPL_NAND_BASE=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_SPL=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),1m(NAND.u-boot),-(NAND.UBI)"
+CONFIG_CMD_UBI=y
+CONFIG_DOS_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETHER=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set