board: siemens: iot2050: Pass DDR size from FSBL

Due to new DDR size introduction, the current logic of determining the
DDR size is not able to get the correct size.

Instead, the DDR size is determined by the FSBL(SEBOOT) then passed to
u-boot through the scratchpad info.

The SEBoot version must be >= D/V01.04.01.02 to support this change.

Also now for some variants, the DDR size may > 2GB, so borrow some code
from the TI evm to iot2050 to support more than 2GB DDR.

Signed-off-by: Baocheng Su <baocheng.su@siemens.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index 85cb999f17fcea1ae53867dfb86c9545a741b089..16082ae2afe73ff232e3d52aa66d70307907a7da 100644 (file)
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -38,6 +38,8 @@ struct iot2050_info {
        u8 mac_addr_cnt;
        u8 mac_addr[8][ARP_HLEN];
        char seboot_version[40 + 1];
+       u8 padding[3];
+       u32 ddr_size_mb;
 } __packed;
 
 /*
@@ -341,25 +343,42 @@ int board_init(void)
 
 int dram_init(void)
 {
-       if (board_is_advanced())
-               gd->ram_size = SZ_2G;
-       else
-               gd->ram_size = SZ_1G;
+       struct iot2050_info *info = IOT2050_INFO_DATA;
+       gd->ram_size = ((phys_size_t)(info->ddr_size_mb)) << 20;
 
        return 0;
 }
 
+ulong board_get_usable_ram_top(ulong total_size)
+{
+       /* Limit RAM used by U-Boot to the DDR low region */
+       if (gd->ram_top > 0x100000000)
+               return 0x100000000;
+
+       return gd->ram_top;
+}
+
 int dram_init_banksize(void)
 {
        dram_init();
 
-       /* Bank 0 declares the memory available in the DDR low region */
-       gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-       gd->bd->bi_dram[0].size = gd->ram_size;
+       if (gd->ram_size > SZ_2G) {
+               /* Bank 0 declares the memory available in the DDR low region */
+               gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+               gd->bd->bi_dram[0].size = SZ_2G;
+
+               /* Bank 1 declares the memory available in the DDR high region */
+               gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+               gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
+       } else {
+               /* Bank 0 declares the memory available in the DDR low region */
+               gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+               gd->bd->bi_dram[0].size = gd->ram_size;
 
-       /* Bank 1 declares the memory available in the DDR high region */
-       gd->bd->bi_dram[1].start = 0;
-       gd->bd->bi_dram[1].size = 0;
+               /* Bank 1 declares the memory available in the DDR high region */
+               gd->bd->bi_dram[1].start = 0;
+               gd->bd->bi_dram[1].size = 0;
+       }
 
        return 0;
 }

diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst
index ee3c5c958464619ab1e70eef4a880d1d4583ad7d..d0c0a412097b12159045154353b56675df8c8f18 100644 (file)
--- a/doc/board/siemens/iot2050.rst
+++ b/doc/board/siemens/iot2050.rst
@@ -29,6 +29,9 @@ The following binaries from that source need to be present in the build folder:
  - seboot_pg1.bin
  - seboot_pg2.bin
 
+Note that SE-Boot D/V01.04.01.02 or greater is required, otherwise the DDR size
+will not be picked up correctly by U-Boot.
+
 When using the watchdog, a related firmware for the R5 core(s) is needed, e.g.
 https://github.com/siemens/k3-rti-wdt. The name and location of the image is
 configured via CONFIG_WDT_K3_RTI_FW_FILE.

diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h
index 0f92e0d25dcef5eed1e08137d526fc34958ec561..5c58c7bbaab45e20616ad4b670dfb97120c08c9a 100644 (file)
--- a/include/configs/iot2050.h
+++ b/include/configs/iot2050.h
@@ -24,6 +24,9 @@
        func(USB, usb, 2)
 #endif
 
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE1            0x880000000
+
 /*
  * This defines all MMC devices, even if the basic variant has no mmc1.
  * The non-supported device will be removed from the boot targets during