From e69d0780394bb48efd41da3e5ada70600cec30f0 Mon Sep 17 00:00:00 2001 From: Pragnesh Patel Date: Sun, 21 Jun 2020 17:22:18 +0530 Subject: [PATCH] mtd: spi-nor: Enable QE bit for ISSI flash in case of SFDP Enable QE bit for ISSI flash chips. QE enablement logic is similar to what Macronix has, so reuse the existing code itself. Signed-off-by: Pragnesh Patel Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 1e3f51d2ac..fdcd830ce4 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1291,7 +1291,7 @@ write_err: return ret; } -#ifdef CONFIG_SPI_FLASH_MACRONIX +#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI) /** * macronix_quad_enable() - set QE bit in Status Register. * @nor: pointer to a 'struct spi_nor' @@ -1969,7 +1969,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, params->quad_enable = spansion_no_read_cr_quad_enable; break; #endif -#ifdef CONFIG_SPI_FLASH_MACRONIX +#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI) case BFPT_DWORD15_QER_SR1_BIT6: params->quad_enable = macronix_quad_enable; break; @@ -2206,8 +2206,9 @@ static int spi_nor_init_params(struct spi_nor *nor, if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD | SNOR_HWCAPS_PP_QUAD)) { switch (JEDEC_MFR(info)) { -#ifdef CONFIG_SPI_FLASH_MACRONIX +#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI) case SNOR_MFR_MACRONIX: + case SNOR_MFR_ISSI: params->quad_enable = macronix_quad_enable; break; #endif -- 2.39.5