From b2c860c6dc5078c710b34a0dec9d6514cf390a85 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Thu, 22 Nov 2018 11:26:17 +0100 Subject: [PATCH] riscv: fix use of incorrectly sized variables The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in several places. Fix this. In addition, BITS_PER_LONG is set to 64 on RV64I systems. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng --- arch/riscv/include/asm/io.h | 6 +++--- arch/riscv/include/asm/posix_types.h | 6 +++--- arch/riscv/include/asm/types.h | 4 ++++ arch/riscv/lib/interrupts.c | 10 +++++----- 4 files changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index f4a76d8720..472814a13e 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -74,12 +74,12 @@ static inline phys_addr_t virt_to_phys(void *vaddr) #define __arch_getb(a) (*(unsigned char *)(a)) #define __arch_getw(a) (*(unsigned short *)(a)) #define __arch_getl(a) (*(unsigned int *)(a)) -#define __arch_getq(a) (*(unsigned long *)(a)) +#define __arch_getq(a) (*(unsigned long long *)(a)) #define __arch_putb(v, a) (*(unsigned char *)(a) = (v)) #define __arch_putw(v, a) (*(unsigned short *)(a) = (v)) #define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) -#define __arch_putq(v, a) (*(unsigned long *)(a) = (v)) +#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v)) #define __raw_writeb(v, a) __arch_putb(v, a) #define __raw_writew(v, a) __arch_putw(v, a) @@ -152,7 +152,7 @@ static inline u32 readl(const volatile void __iomem *addr) static inline u64 readq(const volatile void __iomem *addr) { - u32 val; + u64 val; val = __arch_getq(addr); __iormb(); diff --git a/arch/riscv/include/asm/posix_types.h b/arch/riscv/include/asm/posix_types.h index 7438dbeb03..0fc052082a 100644 --- a/arch/riscv/include/asm/posix_types.h +++ b/arch/riscv/include/asm/posix_types.h @@ -37,10 +37,10 @@ typedef unsigned short __kernel_gid_t; #ifdef __GNUC__ typedef __SIZE_TYPE__ __kernel_size_t; #else -typedef unsigned int __kernel_size_t; +typedef unsigned long __kernel_size_t; #endif -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t; diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index bd8627196d..403cf9a48f 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -21,7 +21,11 @@ typedef unsigned short umode_t; */ #ifdef __KERNEL__ +#ifdef CONFIG_ARCH_RV64I +#define BITS_PER_LONG 64 +#else #define BITS_PER_LONG 32 +#endif #include diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 0a0995a7af..62a16b4da9 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -12,7 +12,7 @@ #include #include -static void _exit_trap(int code, uint epc, struct pt_regs *regs); +static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs); int interrupt_init(void) { @@ -34,9 +34,9 @@ int disable_interrupts(void) return 0; } -uint handle_trap(uint mcause, uint epc, struct pt_regs *regs) +ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs) { - uint is_int; + ulong is_int; is_int = (mcause & MCAUSE_INT); if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) @@ -60,7 +60,7 @@ __attribute__((weak)) void timer_interrupt(struct pt_regs *regs) { } -static void _exit_trap(int code, uint epc, struct pt_regs *regs) +static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) { static const char * const exception_code[] = { "Instruction address misaligned", @@ -70,6 +70,6 @@ static void _exit_trap(int code, uint epc, struct pt_regs *regs) "Load address misaligned" }; - printf("exception code: %d , %s , epc %08x , ra %08lx\n", + printf("exception code: %ld , %s , epc %lx , ra %lx\n", code, exception_code[code], epc, regs->ra); } -- 2.39.5