From aaddce0d35f5ec3f9dc021401c56081a3bd05ebd Mon Sep 17 00:00:00 2001 From: =?utf8?q?Pali=20Roh=C3=A1r?= Date: Tue, 12 Oct 2021 13:19:19 +0200 Subject: [PATCH] arm: a37xx: pci: Do not allow setting bars on PCI Bridge MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit PCI Bridge which represents Aardvark PCIe Root Port does not have configurable bars. So ensure that write operation to bars registers on PCI Bridge is noop and bars registers always contain zero address which indicates that bars are unsupported. After this change U-Boot 'pci bar 0.0.0' command does not show any allocated bars for PCI Bridge device. Signed-off-by: Pali Rohár Fixes: cb056005dc67 ("arm: a37xx: pci: Add support for accessing PCI Bridge on root bus") Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 38eff495ab..ade5ab056f 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -581,6 +581,10 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, if (offset >= 0x10 && offset < 0x34) { data = pcie->cfgcache[(offset - 0x10) / 4]; data = pci_conv_size_to_32(data, value, offset, size); + /* This PCI bridge does not have configurable bars */ + if ((offset & ~3) == PCI_BASE_ADDRESS_0 || + (offset & ~3) == PCI_BASE_ADDRESS_1) + data = 0x0; pcie->cfgcache[(offset - 0x10) / 4] = data; } else if ((offset & ~3) == PCI_ROM_ADDRESS1) { data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG); -- 2.39.5