From 452e33efa8c98c5fa3bb11d1a8b66966df253cdc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:56 -0500 Subject: [PATCH] global: Migrate CONFIG_FM_PLAT_CLK_DIV to CFG Perform a simple rename of CONFIG_FM_PLAT_CLK_DIV to CFG_FM_PLAT_CLK_DIV Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/speed.c | 6 +++--- arch/powerpc/include/asm/config_mpc85xx.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index a6e352ceab..eec071022e 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -67,7 +67,7 @@ void get_sys_info(sys_info_t *sys_info) [14] = 4, /* CC4 PPL / 4 */ }; uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; -#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) uint rcw_tmp; #endif uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -206,7 +206,7 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SEL 0x1c000000 #define FM1_CLK_SHIFT 26 #endif -#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) #if defined(CONFIG_ARCH_T1024) rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; #else @@ -377,7 +377,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_FM_PLAT_CLK_DIV +#ifndef CFG_FM_PLAT_CLK_DIV switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { case 1: sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK]; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 246bcb9fe4..283181ec2d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -147,8 +147,8 @@ #define CONFIG_PME_PLAT_CLK_DIV 2 #define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_FM_PLAT_CLK_DIV 1 -#define CFG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV +#define CFG_FM_PLAT_CLK_DIV 1 +#define CFG_SYS_FM1_CLK CFG_FM_PLAT_CLK_DIV #define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL -- 2.39.5