From 215b4fae518a1ddcd36817cd1e420fa03d058d8e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 9 Jul 2018 15:09:55 -0400 Subject: [PATCH] mips: dbau1x00: Remove this board This platform has been marked as orphan since June of 2016 and should have been removed some time ago. Do so now. Cc: Daniel Schwierzeck Signed-off-by: Tom Rini Reviewed-by: Daniel Schwierzeck --- arch/mips/Kconfig | 11 - arch/mips/mach-au1x00/au1x00_eth.c | 5 - arch/mips/mach-au1x00/include/mach/au1x00.h | 31 -- board/dbau1x00/Kconfig | 46 -- board/dbau1x00/MAINTAINERS | 10 - board/dbau1x00/Makefile | 7 - board/dbau1x00/README | 63 --- board/dbau1x00/dbau1x00.c | 118 ---- board/dbau1x00/lowlevel_init.S | 589 -------------------- configs/dbau1000_defconfig | 21 - configs/dbau1100_defconfig | 21 - configs/dbau1500_defconfig | 21 - configs/dbau1550_defconfig | 16 - configs/dbau1550_el_defconfig | 17 - include/configs/dbau1x00.h | 172 ------ 15 files changed, 1148 deletions(-) delete mode 100644 board/dbau1x00/Kconfig delete mode 100644 board/dbau1x00/MAINTAINERS delete mode 100644 board/dbau1x00/Makefile delete mode 100644 board/dbau1x00/README delete mode 100644 board/dbau1x00/dbau1x00.c delete mode 100644 board/dbau1x00/lowlevel_init.S delete mode 100644 configs/dbau1000_defconfig delete mode 100644 configs/dbau1100_defconfig delete mode 100644 configs/dbau1500_defconfig delete mode 100644 configs/dbau1550_defconfig delete mode 100644 configs/dbau1550_el_defconfig delete mode 100644 include/configs/dbau1x00.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 31b622ff51..01c4e1628d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -52,16 +52,6 @@ config TARGET_VCT select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD -config TARGET_DBAU1X00 - bool "Support dbau1x00" - select MIPS_TUNE_4KC - select ROM_EXCEPTION_VECTORS - select SUPPORTS_BIG_ENDIAN - select SUPPORTS_CPU_MIPS32_R1 - select SUPPORTS_CPU_MIPS32_R2 - select SUPPORTS_LITTLE_ENDIAN - select SYS_MIPS_CACHE_INIT_RAM_LOAD - config TARGET_PB1X00 bool "Support pb1x00" select MIPS_TUNE_4KC @@ -131,7 +121,6 @@ config TARGET_XILFPGA endchoice -source "board/dbau1x00/Kconfig" source "board/imgtec/boston/Kconfig" source "board/imgtec/malta/Kconfig" source "board/imgtec/xilfpga/Kconfig" diff --git a/arch/mips/mach-au1x00/au1x00_eth.c b/arch/mips/mach-au1x00/au1x00_eth.c index 84a1f59ba0..ef9be891ec 100644 --- a/arch/mips/mach-au1x00/au1x00_eth.c +++ b/arch/mips/mach-au1x00/au1x00_eth.c @@ -27,15 +27,10 @@ #define ETH0_BASE AU1500_ETH0_BASE #define MAC0_ENABLE AU1500_MAC0_ENABLE #else -#ifdef CONFIG_SOC_AU1550 -#define ETH0_BASE AU1550_ETH0_BASE -#define MAC0_ENABLE AU1550_MAC0_ENABLE -#else #error "No valid cpu set" #endif #endif #endif -#endif #include #include diff --git a/arch/mips/mach-au1x00/include/mach/au1x00.h b/arch/mips/mach-au1x00/include/mach/au1x00.h index e242489978..1fabcba65d 100644 --- a/arch/mips/mach-au1x00/include/mach/au1x00.h +++ b/arch/mips/mach-au1x00/include/mach/au1x00.h @@ -118,27 +118,6 @@ static __inline__ int au_ffs(int x) #define CP0_DEBUG $23 /* SDRAM Controller */ -#ifdef CONFIG_SOC_AU1550 - -#define MEM_SDMODE0 0xB4000800 -#define MEM_SDMODE1 0xB4000808 -#define MEM_SDMODE2 0xB4000810 - -#define MEM_SDADDR0 0xB4000820 -#define MEM_SDADDR1 0xB4000828 -#define MEM_SDADDR2 0xB4000830 - -#define MEM_SDCONFIGA 0xB4000840 -#define MEM_SDCONFIGB 0xB4000848 -#define MEM_SDPRECMD 0xB40008c0 -#define MEM_SDAUTOREF 0xB40008c8 - -#define MEM_SDWRMD0 0xB4000880 -#define MEM_SDWRMD1 0xB4000888 -#define MEM_SDWRMD2 0xB4000890 - -#else /* CONFIG_SOC_AU1550 */ - #define MEM_SDMODE0 0xB4000000 #define MEM_SDMODE1 0xB4000004 #define MEM_SDMODE2 0xB4000008 @@ -155,8 +134,6 @@ static __inline__ int au_ffs(int x) #define MEM_SDWRMD1 0xB4000028 #define MEM_SDWRMD2 0xB400002C -#endif /* CONFIG_SOC_AU1550 */ - #define MEM_SDSLEEP 0xB4000030 #define MEM_SDSMCKE 0xB4000034 @@ -483,8 +460,6 @@ static __inline__ int au_ffs(int x) #define AU1500_ETH0_BASE 0xB1500000 #define AU1500_ETH1_BASE 0xB1510000 #define AU1100_ETH0_BASE 0xB0500000 -#define AU1550_ETH0_BASE 0xB0500000 -#define AU1550_ETH1_BASE 0xB0510000 /* 4 byte offsets from AU1000_ETH_BASE */ #define MAC_CONTROL 0x0 @@ -534,8 +509,6 @@ static __inline__ int au_ffs(int x) #define AU1500_MAC0_ENABLE 0xB1520000 #define AU1500_MAC1_ENABLE 0xB1520004 #define AU1100_MAC0_ENABLE 0xB0520000 -#define AU1550_MAC0_ENABLE 0xB0520000 -#define AU1550_MAC1_ENABLE 0xB0520004 #define MAC_EN_CLOCK_ENABLE (1<<0) #define MAC_EN_RESET0 (1<<1) @@ -995,11 +968,7 @@ static __inline__ int au_ffs(int x) #define DB1000_BCSR_ADDR 0xAE000000 #define DB1550_BCSR_ADDR 0xAF000000 -#ifdef CONFIG_DBAU1550 -#define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR -#else #define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR -#endif #ifdef CONFIG_SOC_AU1500 /* Au1500 PCI Controller */ diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig deleted file mode 100644 index 448176d8ba..0000000000 --- a/board/dbau1x00/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -if TARGET_DBAU1X00 - -config SYS_BOARD - default "dbau1x00" - -config SYS_SOC - default "au1x00" - -config SYS_CONFIG_NAME - default "dbau1x00" - -config SYS_TEXT_BASE - default 0xbfc00000 - -config SYS_DCACHE_SIZE - default 16384 - -config SYS_DCACHE_LINE_SIZE - default 32 - -config SYS_ICACHE_SIZE - default 16384 - -config SYS_ICACHE_LINE_SIZE - default 32 - -menu "dbau1x00 board options" - -choice - prompt "Select au1x00 SoC type" - optional - -config DBAU1100 - bool "Select AU1100" - -config DBAU1500 - bool "Select AU1500" - -config DBAU1550 - bool "Select AU1550" - -endchoice - -endmenu - -endif diff --git a/board/dbau1x00/MAINTAINERS b/board/dbau1x00/MAINTAINERS deleted file mode 100644 index 21853ed2fe..0000000000 --- a/board/dbau1x00/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -DBAU1X00 BOARD -#M: - -S: Orphan (since 2016-06) -F: board/dbau1x00/ -F: include/configs/dbau1x00.h -F: configs/dbau1000_defconfig -F: configs/dbau1100_defconfig -F: configs/dbau1500_defconfig -F: configs/dbau1550_defconfig -F: configs/dbau1550_el_defconfig diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile deleted file mode 100644 index 0ea56ef59c..0000000000 --- a/board/dbau1x00/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = dbau1x00.o -obj-y += lowlevel_init.o diff --git a/board/dbau1x00/README b/board/dbau1x00/README deleted file mode 100644 index b1e9494118..0000000000 --- a/board/dbau1x00/README +++ /dev/null @@ -1,63 +0,0 @@ -By Thomas.Lange@corelatus.se 2004-Oct-05 ----------------------------------------- -DbAu1xx0 are development boards from AMD containing -an Alchemy AU1xx0 series cpu with mips32 core. -Existing cpu:s are Au1000, Au1100, Au1500 and Au1550 - -Limitations & comments ----------------------- -Support was originally big endian only. -I have not tested, but several u-boot users report working -configurations in little endian mode. - -I named the board dbau1x00, to allow -support for all three development boards -( dbau1000, dbau1100 and dbau1500 ). -Now there is a new board called dbau1550 also, which -should be supported RSN. - -I only have a dbau1000, so my testing is limited -to this board. - -The board has two different flash banks, that can -be selected via dip switch. This makes it possible -to test new bootloaders without thrashing the YAMON -boot loader delivered with board. - -NOTE! When you switch between the two boot flashes, the -base addresses will be swapped. -Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has -to match the address where u-boot is located when you -actually launch. - -Ethernet only supported for mac0. - -PCMCIA only supported for slot 0, only 3.3V. - -PCMCIA IDE tested with Sandisk Compact Flash and -IBM microdrive. - -################################### -######## NOTE!!!!!! ######### -################################### -If you partition a disk on another system (e.g. laptop), -all bytes will be swapped on 16bit level when using -PCMCIA and running cpu in big endian mode!!!! - -This is probably due to an error in Au1000 chip. - -Solution: - -a) Boot via network and partition disk directly from -dbau1x00. The endian will then be correct. - -b) Partition disk on "laptop" and fill it with all files -you need. Then write a simple program that endian swaps -whole disk, - -Example: -Original "laptop" byte order: -B0 B1 B2 B3 B4 B5 B6 B7 B8 B9... - -Dbau1000 byte order will then be: -B1 B0 B3 B2 B5 B4 B7 B6 B9 B8... diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c deleted file mode 100644 index 1e62753b30..0000000000 --- a/board/dbau1x00/dbau1x00.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 - * Thomas.Lange@corelatus.se - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* Sdram is setup by assembler code */ - /* If memory could be changed, we should return the true value here */ - gd->ram_size = MEM_SIZE * 1024 * 1024; - - return 0; -} - -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 - -/* In arch/mips/cpu/cpu.c */ -void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); - -int checkboard (void) -{ -#ifdef CONFIG_IDE_PCMCIA - u16 status; - volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10); -#endif /* CONFIG_IDE_PCMCIA */ - volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC); - volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; - u32 proc_id; - - *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - - proc_id = read_c0_prid(); - - switch (proc_id >> 24) { - case 0: - puts ("Board: Merlot (DbAu1000)\n"); - printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 1: - puts ("Board: DbAu1500\n"); - printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 2: - puts ("Board: DbAu1100\n"); - printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 3: - puts ("Board: DbAu1550\n"); - printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - default: - printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); - } - - set_io_port_base(0); - -#ifdef CONFIG_IDE_PCMCIA - /* Enable 3.3 V on slot 0 ( VCC ) - No 5V */ - status = 4; - *pcmcia_bcsr = status; - - status |= BCSR_PCMCIA_PC0DRVEN; - *pcmcia_bcsr = status; - au_sync(); - - udelay(300*1000); - - status |= BCSR_PCMCIA_PC0RST; - *pcmcia_bcsr = status; - au_sync(); - - udelay(100*1000); - - /* PCMCIA is on a 36 bit physical address. - We need to map it into a 32 bit addresses */ - -#if 0 - /* We dont need theese unless we run whole pcmcia package */ - write_one_tlb(20, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */ - 0x3C000017, /* Lo0 */ - 0x3C200017); /* Lo1 */ - - write_one_tlb(21, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */ - 0x3D000017, /* Lo0 */ - 0x3D200017); /* Lo1 */ -#endif /* 0 */ - write_one_tlb(22, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */ - 0x3E000017, /* Lo0 */ - 0x3E200017); /* Lo1 */ -#endif /* CONFIG_IDE_PCMCIA */ - - /* Release reset of ethernet PHY chips */ - /* Always do this, because linux does not know about it */ - *phy = 3; - - return 0; -} diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S deleted file mode 100644 index 409f8ee477..0000000000 --- a/board/dbau1x00/lowlevel_init.S +++ /dev/null @@ -1,589 +0,0 @@ -/* Memory sub-system initialization code */ - -#include -#include -#include -#include - -#define AU1500_SYS_ADDR 0xB1900000 -#define sys_endian 0x0038 -#define CP0_Config0 $16 -#define CPU_SCALE ((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */ -#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000) - - .text - .set noreorder - .set mips32 - - .globl lowlevel_init -lowlevel_init: - /* - * Step 1) Establish CPU endian mode. - * Db1500-specific: - * Switch S1.1 Off(bit7 reads 1) is Little Endian - * Switch S1.1 On (bit7 reads 0) is Big Endian - */ -#ifdef CONFIG_DBAU1550 - li t0, MEM_STCFG2 - li t1, 0x00000040 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x10c03f00 - sw t1, 0(t0) -#else - li t0, MEM_STCFG1 - li t1, 0x00000080 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x10c03f00 - sw t1, 0(t0) -#endif - - li t0, DB1XX0_BCSR_ADDR - lw t1,8(t0) - andi t1,t1,0x80 - beq zero,t1,big_endian - nop -little_endian: - - /* Change Au1 core to little endian */ - li t0, AU1500_SYS_ADDR - li t1, 1 - sw t1, sys_endian(t0) - mfc0 t2, CP0_CONFIG - mtc0 t2, CP0_CONFIG - nop - nop - - /* Big Endian is default so nothing to do but fall through */ - -big_endian: - - /* - * Step 2) Establish Status Register - * (set BEV, clear ERL, clear EXL, clear IE) - */ - li t1, 0x00400000 - mtc0 t1, CP0_STATUS - - /* - * Step 3) Establish CP0 Config0 - * (set OD, set K0=3) - */ - li t1, 0x00080003 - mtc0 t1, CP0_CONFIG - - /* - * Step 4) Disable Watchpoint facilities - */ - li t1, 0x00000000 - mtc0 t1, CP0_WATCHLO - mtc0 t1, CP0_IWATCHLO - /* - * Step 5) Disable the performance counters - */ - mtc0 zero, CP0_PERFORMANCE - nop - - /* - * Step 6) Establish EJTAG Debug register - */ - mtc0 zero, CP0_DEBUG - nop - - /* - * Step 7) Establish Cause - * (set IV bit) - */ - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* Establish Wired (and Random) */ - mtc0 zero, CP0_WIRED - nop - -#ifdef CONFIG_DBAU1550 - /* No workaround if running from ram */ - lui t0, 0xffc0 - lui t3, 0xbfc0 - and t1, ra, t0 - bne t1, t3, noCacheJump - nop - - /*** From AMD YAMON ***/ - /* - * Step 8) Initialize the caches - */ - li t0, (16*1024) - li t1, 32 - li t2, 0x80000000 - addu t3, t0, t2 -cacheloop: - cache 0, 0(t2) - cache 1, 0(t2) - addu t2, t1 - bne t2, t3, cacheloop - nop - - /* Save return address */ - move t3, ra - - /* Run from cacheable space now */ - bal cachehere - nop -cachehere: - li t1, ~0x20000000 /* convert to KSEG0 */ - and t0, ra, t1 - addi t0, 5*4 /* 5 insns beyond cachehere */ - jr t0 - nop - - /* Restore return address */ - move ra, t3 - - /* - * Step 9) Initialize the TLB - */ - li t0, 0 # index value - li t1, 0x00000000 # entryhi value - li t2, 32 # 32 entries - -tlbloop: - /* Probe TLB for matching EntryHi */ - mtc0 t1, CP0_ENTRYHI - tlbp - nop - - /* Examine Index[P], 1=no matching entry */ - mfc0 t3, CP0_INDEX - li t4, 0x80000000 - and t3, t4, t3 - addiu t1, t1, 1 # increment t1 (asid) - beq zero, t3, tlbloop - nop - - /* Initialize the TLB entry */ - mtc0 t0, CP0_INDEX - mtc0 zero, CP0_ENTRYLO0 - mtc0 zero, CP0_ENTRYLO1 - mtc0 zero, CP0_PAGEMASK - tlbwi - - /* Do it again */ - addiu t0, t0, 1 - bne t0, t2, tlbloop - nop - -#endif /* CONFIG_DBAU1550 */ - - /* First setup pll:s to make serial work ok */ - /* We have a 12 MHz crystal */ - li t0, SYS_CPUPLL - li t1, CPU_SCALE /* CPU clock */ - sw t1, 0(t0) - sync - nop - nop - - /* wait 1mS for clocks to settle */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - /* Setup AUX PLL */ - li t0, SYS_AUXPLL - li t1, 0x20 /* 96 MHz */ - sw t1, 0(t0) /* aux pll */ - sync - -#ifdef CONFIG_DBAU1550 - /* Static memory controller */ - /* RCE0 - can not change while fetching, do so from icache */ - move t2, ra /* Store return address */ - bal getAddr - nop - -getAddr: - move t1, ra - move ra, t2 /* Move return addess back */ - - cache 0x14,0(t1) - cache 0x14,32(t1) - /*** /From YAMON ***/ - -noCacheJump: -#endif /* CONFIG_DBAU1550 */ - -#ifdef CONFIG_DBAU1550 - li t0, MEM_STTIME0 - li t1, 0x040181D7 - sw t1, 0(t0) - - /* RCE0 AMD MirrorBit Flash (?) */ - li t0, MEM_STCFG0 - li t1, 0x00000003 - sw t1, 0(t0) - - li t0, MEM_STADDR0 - li t1, 0x11803E00 - sw t1, 0(t0) -#else /* CONFIG_DBAU1550 */ - li t0, MEM_STTIME0 - li t1, 0x040181D7 - sw t1, 0(t0) - - /* RCE0 AMD 29LV640M MirrorBit Flash */ - li t0, MEM_STCFG0 - li t1, 0x00000013 - sw t1, 0(t0) - - li t0, MEM_STADDR0 - li t1, 0x11E03F80 - sw t1, 0(t0) -#endif /* CONFIG_DBAU1550 */ - - /* RCE1 CPLD Board Logic */ - li t0, MEM_STCFG1 - li t1, 0x00000080 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x10c03f00 - sw t1, 0(t0) - -#ifdef CONFIG_DBAU1550 - /* RCE2 CPLD Board Logic */ - li t0, MEM_STCFG2 - li t1, 0x00000040 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x10c03f00 - sw t1, 0(t0) -#else - li t0, MEM_STCFG2 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x00000000 - sw t1, 0(t0) -#endif - - /* RCE3 PCMCIA 250ns */ - li t0, MEM_STCFG3 - li t1, 0x00000002 - sw t1, 0(t0) - - li t0, MEM_STTIME3 - li t1, 0x280E3E07 - sw t1, 0(t0) - - li t0, MEM_STADDR3 - li t1, 0x10000000 - sw t1, 0(t0) - - sync - - /* Set peripherals to a known state */ - li t0, IC0_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC0_CFG0CLR - sw t1, 0(t0) - - li t0, IC0_CFG1CLR - sw t1, 0(t0) - - li t0, IC0_CFG2CLR - sw t1, 0(t0) - - li t0, IC0_SRCSET - sw t1, 0(t0) - - li t0, IC0_ASSIGNSET - sw t1, 0(t0) - - li t0, IC0_WAKECLR - sw t1, 0(t0) - - li t0, IC0_RISINGCLR - sw t1, 0(t0) - - li t0, IC0_FALLINGCLR - sw t1, 0(t0) - - li t0, IC0_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, IC1_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC1_CFG0CLR - sw t1, 0(t0) - - li t0, IC1_CFG1CLR - sw t1, 0(t0) - - li t0, IC1_CFG2CLR - sw t1, 0(t0) - - li t0, IC1_SRCSET - sw t1, 0(t0) - - li t0, IC1_ASSIGNSET - sw t1, 0(t0) - - li t0, IC1_WAKECLR - sw t1, 0(t0) - - li t0, IC1_RISINGCLR - sw t1, 0(t0) - - li t0, IC1_FALLINGCLR - sw t1, 0(t0) - - li t0, IC1_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, SYS_FREQCTRL0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_FREQCTRL1 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_CLKSRC - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_PININPUTEN - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, 0xB1100100 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, 0xB1400100 - li t1, 0x00000000 - sw t1, 0(t0) - - - li t0, SYS_WAKEMSK - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_WAKESRC - li t1, 0x00000000 - sw t1, 0(t0) - - /* wait 1mS before setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - -#ifdef CONFIG_DBAU1550 -/* SDCS 0,1,2 DDR SDRAM */ - li t0, MEM_SDMODE0 - li t1, 0x04276221 - sw t1, 0(t0) - - li t0, MEM_SDMODE1 - li t1, 0x04276221 - sw t1, 0(t0) - - li t0, MEM_SDMODE2 - li t1, 0x04276221 - sw t1, 0(t0) - - li t0, MEM_SDADDR0 - li t1, 0xe21003f0 - sw t1, 0(t0) - - li t0, MEM_SDADDR1 - li t1, 0xe21043f0 - sw t1, 0(t0) - - li t0, MEM_SDADDR2 - li t1, 0xe21083f0 - sw t1, 0(t0) - - sync - - li t0, MEM_SDCONFIGA - li t1, 0x9030060a /* Program refresh - disabled */ - sw t1, 0(t0) - sync - - li t0, MEM_SDCONFIGB - li t1, 0x00028000 - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD /* Precharge all */ - li t1, 0 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x40000000 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x40000000 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD2 - li t1, 0x40000000 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x00000063 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x00000063 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD2 - li t1, 0x00000063 - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD /* Precharge all */ - sw zero, 0(t0) - sync - - /* Issue 2 autoref */ - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - - /* Enable refresh */ - li t0, MEM_SDCONFIGA - li t1, 0x9830060a /* Program refresh - enabled */ - sw t1, 0(t0) - sync - -#else /* CONFIG_DBAU1550 */ -/* SDCS 0,1 SDRAM */ - li t0, MEM_SDMODE0 - li t1, 0x005522AA - sw t1, 0(t0) - - li t0, MEM_SDMODE1 - li t1, 0x005522AA - sw t1, 0(t0) - - li t0, MEM_SDMODE2 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_SDADDR0 - li t1, 0x001003F8 - sw t1, 0(t0) - - - li t0, MEM_SDADDR1 - li t1, 0x001023F8 - sw t1, 0(t0) - - li t0, MEM_SDADDR2 - li t1, 0x00000000 - sw t1, 0(t0) - - sync - - li t0, MEM_SDREFCFG - li t1, 0x64000C24 /* Disable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD - sw zero, 0(t0) - sync - - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - sw zero, 0(t0) - sync - - li t0, MEM_SDREFCFG - li t1, 0x66000C24 /* Enable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x00000033 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x00000033 - sw t1, 0(t0) - sync - -#endif /* CONFIG_DBAU1550 */ - /* wait 1mS after setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - - li t0, SYS_PINFUNC - li t1, 0x00008080 - sw t1, 0(t0) - - li t0, SYS_TRIOUTCLR - li t1, 0x00001FFF - sw t1, 0(t0) - - li t0, SYS_OUTPUTCLR - li t1, 0x00008000 - sw t1, 0(t0) - sync - - jr ra - nop diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig deleted file mode 100644 index 4161262bc9..0000000000 --- a/configs/dbau1000_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0xBFC00000 -CONFIG_TARGET_DBAU1X00=y -CONFIG_SYS_EXTRA_OPTIONS="DBAU1000" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="DbAu1xx0 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_RUN is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_MAC_PARTITION=y -# CONFIG_ISO_PARTITION is not set -CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig deleted file mode 100644 index 96305e40f8..0000000000 --- a/configs/dbau1100_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0xBFC00000 -CONFIG_TARGET_DBAU1X00=y -CONFIG_DBAU1100=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="DbAu1xx0 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_RUN is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_MAC_PARTITION=y -# CONFIG_ISO_PARTITION is not set -CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig deleted file mode 100644 index eb83a3dbbb..0000000000 --- a/configs/dbau1500_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0xBFC00000 -CONFIG_TARGET_DBAU1X00=y -CONFIG_DBAU1500=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="DbAu1xx0 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_RUN is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_MAC_PARTITION=y -# CONFIG_ISO_PARTITION is not set -CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig deleted file mode 100644 index 619874a98f..0000000000 --- a/configs/dbau1550_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0xBFC00000 -CONFIG_TARGET_DBAU1X00=y -CONFIG_DBAU1550=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="DbAu1xx0 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_RUN is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig deleted file mode 100644 index b1e448073b..0000000000 --- a/configs/dbau1550_el_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0xBFC00000 -CONFIG_TARGET_DBAU1X00=y -CONFIG_DBAU1550=y -CONFIG_SYS_LITTLE_ENDIAN=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="DbAu1xx0 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_RUN is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_MTD_NOR_FLASH=y diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h deleted file mode 100644 index 82860bbaa8..0000000000 --- a/include/configs/dbau1x00.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * This file contains the configuration parameters for the dbau1x00 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ - -#ifdef CONFIG_DBAU1000 -/* Also known as Merlot */ -#define CONFIG_SOC_AU1000 1 -#else -#ifdef CONFIG_DBAU1100 -#define CONFIG_SOC_AU1100 1 -#else -#ifdef CONFIG_DBAU1500 -#define CONFIG_SOC_AU1500 1 -#else -#ifdef CONFIG_DBAU1550 -/* Cabernet */ -#define CONFIG_SOC_AU1550 1 -#else -#error "No valid board set" -#endif -#endif -#endif -#endif - -/* valid baudrates */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "panic=1\0" \ - "bootfile=/tftpboot/vmlinux.srec\0" \ - "load=tftp 80500000 ${u-boot}\0" \ - "" - -#ifdef CONFIG_DBAU1550 -/* Boot from flash by default, revert to bootp */ -#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" -#else /* CONFIG_DBAU1550 */ -#define CONFIG_BOOTCOMMAND "bootp;bootm" -#endif /* CONFIG_DBAU1550 */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MALLOC_LEN 128*1024 - -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 - -#define CONFIG_SYS_MHZ 396 - -#if (CONFIG_SYS_MHZ % 12) != 0 -#error "Invalid CPU frequency - must be multiple of 12!" -#endif - -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ - -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#ifdef CONFIG_DBAU1550 - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ - -#else /* CONFIG_DBAU1550 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ - -#endif /* CONFIG_DBAU1550 */ - -#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -/* We boot from this flash, selected with dip switch */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR 0xB0030000 -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_FLASH_16BIT - -#define CONFIG_NR_DRAM_BANKS 2 - -#ifdef CONFIG_DBAU1550 -#define MEM_SIZE 192 -#else -#define MEM_SIZE 64 -#endif - -#define CONFIG_MEMSIZE_IN_BYTES - -#ifndef CONFIG_DBAU1550 -/*---ATA PCMCIA ------------------------------------*/ -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 -#define CONFIG_PCMCIA_SLOT_A - -#define CONFIG_ATAPI 1 - -/* We run CF in "true ide" mode or a harddrive via pcmcia */ -#define CONFIG_IDE_PCMCIA 1 - -/* We only support one slot for now */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET 8 - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET 0 - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 -#endif /* CONFIG_DBAU1550 */ - -#endif /* __CONFIG_H */ -- 2.39.5