From 048aff6d2621df2654dce6f833a2cf843358486a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 4 Jun 2021 13:51:12 +0800 Subject: [PATCH] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit All the device nodes that refer to plic0 as their interrupt parent have 2 cells encoded in their interrupts property, but plic0 only provides 1 cell in #interrupt-cells which is incorrect. Signed-off-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/ae350_32.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 0917b83108..70576846f2 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -135,7 +135,7 @@ plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupt-controller; reg = <0xe4000000 0x2000000>; riscv,ndev=<71>; -- 2.39.5