From 01aabf97d1f08694ed511785638685cbee21e597 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 19 Feb 2019 00:37:20 +0100 Subject: [PATCH] ARM: dts: stm32: Migrate U-boot nodes to U-boot DT files for stm32f7 In order to prepare and ease future DT synchronization with kernel DT, migrate all U-boot specific nodes/properties/addons to U-boot DT files. Migrate also DT nodes which are not yet available on kernel DT side as ethernet, ltdc and qspi nodes. Fix ethernet_mii pins and add missing qspi_pins for stm32746g-eval Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32746g-eval-u-boot.dtsi | 171 +++++++++++++++ arch/arm/dts/stm32746g-eval.dts | 142 +------------ arch/arm/dts/stm32f7-u-boot.dtsi | 143 +++++++++++-- arch/arm/dts/stm32f746-disco-u-boot.dtsi | 251 +++++++++++++++++++++++ arch/arm/dts/stm32f746-disco.dts | 217 -------------------- arch/arm/dts/stm32f746.dtsi | 60 +----- arch/arm/dts/stm32f769-disco-u-boot.dtsi | 165 +++++++++++++++ arch/arm/dts/stm32f769-disco.dts | 167 --------------- 8 files changed, 718 insertions(+), 598 deletions(-) create mode 100644 arch/arm/dts/stm32746g-eval-u-boot.dtsi create mode 100644 arch/arm/dts/stm32f746-disco-u-boot.dtsi create mode 100644 arch/arm/dts/stm32f769-disco-u-boot.dtsi diff --git a/arch/arm/dts/stm32746g-eval-u-boot.dtsi b/arch/arm/dts/stm32746g-eval-u-boot.dtsi new file mode 100644 index 0000000000..27d3c8a445 --- /dev/null +++ b/arch/arm/dts/stm32746g-eval-u-boot.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +/{ + chosen { + bootargs = "root=/dev/mmcblk0p1 rw rootwait"; + }; + + aliases { + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + mmc0 = &sdio; + spi0 = &qspi; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioc 13 0>; + }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpiof 10 0>; + }; +}; + +&fmc { + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + */ + bank1: bank@0 { + u-boot,dm-pre-reloc; + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + st,sdram-refcount = <1539>; + }; +}; + +&mac { + phy-mode = "mii"; +}; + +&pinctrl { + ethernet_mii: mii@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + pins { + pinmux = , /* FMC_D31 */ + , /* FMC_D30*/ + , /* FMC_D29 */ + , /* FMC_D28 */ + , /* FMC_D27 */ + , /* FMC_D26 */ + , /* FMC_D25 */ + , /* FMC_D24 */ + , /* FMC_D23 */ + , /* FMC_D22 */ + , /* FMC_D21 */ + , /* FMC_D20 */ + , /* FMC_D19 */ + , /* FMC_D18 */ + , /* FMC_D17 */ + , /* FMC_D16 */ + + , /* FMC_D15 */ + , /* FMC_D14*/ + , /* FMC_D13 */ + ,/* FMC_D12 */ + ,/* FMC_D11 */ + ,/* FMC_D10 */ + , /* FMC_D9 */ + , /* FMC_D8 */ + , /* FMC_D7 */ + , /* FMC_D6 */ + , /* FMC_D5*/ + , /* FMC_D4 */ + , /* FMC_D3 */ + , /* FMC_D2 */ + , /* FMC_D1 */ + , /* FMC_D0 */ + + , /* FMC_NBL3 */ + , /* FMC_NBL2 */ + , /* FMC_NBL1 */ + , /* FMC_NBL0 */ + + , /* FMC_A15 FMC_BA1 */ + , /* FMC_A14 FMC_BA0*/ + + , /* FMC_A11 */ + , /* FMC_A10 */ + , /* FMC_A9 */ + , /* FMC_A8 */ + , /* FMC_A7 */ + , /* FMC_A6 */ + , /* FUNC_FMC_A5 */ + , /* FMC_A4 */ + , /* FMC_A3 */ + , /* FMC_A2 */ + , /* FMC_A1 */ + , /* FMC_A0 */ + + ,/* FMC_SDNE0 */ + , /* FMC_SDNWE */ + , /* FMC_SDNRAS */ + , /* FMC_SDNCAS */ + , /* FMC_SDCKE0 */ + ; /* FMC_SDCLK */ + slew-rate = <2>; + }; + }; + + qspi_pins: qspi@0 { + pins { + pinmux = , + , + , + , + , + ; + slew-rate = <2>; + }; + }; +}; + +&qspi { + qflash0: n25q512a { + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <108000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts index 4f6d38accc..94df80f69d 100644 --- a/arch/arm/dts/stm32746g-eval.dts +++ b/arch/arm/dts/stm32746g-eval.dts @@ -53,7 +53,6 @@ compatible = "st,stm32f746g-eval", "st,stm32f746"; chosen { - bootargs = "root=/dev/mmcblk0p1 rw rootwait"; stdout-path = "serial0:115200n8"; }; @@ -63,30 +62,6 @@ aliases { serial0 = &usart1; - spi0 = &qspi; - mmc0 = &sdio; - /* Aliases for gpios so as to use sequence */ - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; - }; - - led1 { - compatible = "st,led1"; - led-gpio = <&gpiof 10 0>; - }; - - button1 { - compatible = "st,button1"; - button-gpio = <&gpioc 13 0>; }; }; @@ -97,7 +72,7 @@ &pinctrl { usart1_pins_a: usart1@0 { pins1 { - pinmux = ; + pinmux = ; bias-disable; drive-push-pull; slew-rate = <2>; @@ -107,88 +82,6 @@ bias-disable; }; }; - - ethernet_mii: mii@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - fmc_pins: fmc@0 { - pins { - pinmux = , /* FMC_D31 */ - , /* FMC_D30*/ - , /* FMC_D29 */ - , /* FMC_D28 */ - , /* FMC_D27 */ - , /* FMC_D26 */ - , /* FMC_D25 */ - , /* FMC_D24 */ - , /* FMC_D23 */ - , /* FMC_D22 */ - , /* FMC_D21 */ - , /* FMC_D20 */ - , /* FMC_D19 */ - , /* FMC_D18 */ - , /* FMC_D17 */ - , /* FMC_D16 */ - - , /* FMC_D15 */ - , /* FMC_D14*/ - , /* FMC_D13 */ - ,/* FMC_D12 */ - ,/* FMC_D11 */ - ,/* FMC_D10 */ - , /* FMC_D9 */ - , /* FMC_D8 */ - , /* FMC_D7 */ - , /* FMC_D6 */ - , /* FMC_D5*/ - , /* FMC_D4 */ - , /* FMC_D3 */ - , /* FMC_D2 */ - , /* FMC_D1 */ - , /* FMC_D0 */ - - , /* FMC_NBL3 */ - , /* FMC_NBL2 */ - , /* FMC_NBL1 */ - , /* FMC_NBL0 */ - - , /* FMC_A15 FMC_BA1 */ - , /* FMC_A14 FMC_BA0*/ - - , /* FMC_A11 */ - , /* FMC_A10 */ - , /* FMC_A9 */ - , /* FMC_A8 */ - , /* FMC_A7 */ - , /* FMC_A6 */ - , /* FUNC_FMC_A5 */ - , /* FMC_A4 */ - , /* FMC_A3 */ - , /* FMC_A2 */ - , /* FMC_A1 */ - , /* FMC_A0 */ - - ,/* FMC_SDNE0 */ - , /* FMC_SDNWE */ - , /* FMC_SDNRAS */ - , /* FMC_SDNCAS */ - , /* FMC_SDCKE0 */ - ; /* FMC_SDCLK */ - slew-rate = <2>; - }; - }; }; &usart1 { @@ -197,39 +90,6 @@ status = "okay"; }; -&mac { - status = "okay"; - pinctrl-0 = <ðernet_mii>; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&fmc { - pinctrl-0 = <&fmc_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* - * Memory configuration from sdram datasheet IS42S32800G-6BLI - */ - bank1: bank@0 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; - st,sdram-refcount = <1539>; - }; -}; - &sdio { status = "okay"; pinctrl-names = "default", "opendrain"; diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 4a677192a2..cf0cc3b408 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -1,12 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ + /{ soc { - timer5: timer@40000c00 { + u-boot,dm-pre-reloc; + + fmc: fmc@A0000000 { + compatible = "st,stm32-fmc"; + reg = <0xA0000000 0x1000>; + clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; u-boot,dm-pre-reloc; }; + + mac: ethernet@40028000 { + compatible = "st,stm32-dwmac"; + reg = <0x40028000 0x8000>; + reg-names = "stmmaceth"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>, + <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>, + <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>; + interrupts = <61>, <62>; + interrupt-names = "macirq", "eth_wake_irq"; + snps,pbl = <8>; + snps,mixed-burst; + dma-ranges; + pinctrl-0 = <ðernet_mii>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + status = "okay"; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + + qspi: quadspi@A0001000 { + compatible = "st,stm32-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = <92>; + spi-max-frequency = <108000000>; + clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>; + resets = <&rcc STM32F7_AHB3_RESET(QSPI)>; + pinctrl-0 = <&qspi_pins>; + + status = "okay"; + }; }; }; +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&gpioa { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiob { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioc { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiod { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioe { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiof { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiog { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioh { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioi { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioj { + compatible = "st,stm32-gpio"; +}; + +&gpiok { + compatible = "st,stm32-gpio"; +}; + &pinctrl { + u-boot,dm-pre-reloc; + + fmc_pins: fmc@0 { + u-boot,dm-pre-reloc; + pins + { + u-boot,dm-pre-reloc; + }; + }; + usart1_pins_a: usart1@0 { u-boot,dm-pre-reloc; pins1 { @@ -16,25 +136,20 @@ u-boot,dm-pre-reloc; }; }; - fmc_pins: fmc@0 { - u-boot,dm-pre-reloc; - pins - { - u-boot,dm-pre-reloc; - }; - }; }; -&fmc { - bank1: bank@0 { - u-boot,dm-pre-reloc; - }; +&pwrcfg { + u-boot,dm-pre-reloc; }; -&pwrcfg { +&rcc { u-boot,dm-pre-reloc; }; -&clk_hse { +&timer5 { + u-boot,dm-pre-reloc; +}; + +&usart1 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi new file mode 100644 index 0000000000..ceab5e5933 --- /dev/null +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +/{ + chosen { + bootargs = "root=/dev/ram rdinit=/linuxrc"; + }; + + aliases { + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + mmc0 = &sdio; + spi0 = &qspi; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiok 3 0>; + status = "okay"; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioi 11 0>; + }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpioi 1 0>; + }; + + panel-rgb@0 { + compatible = "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpioi 12 0>; + status = "okay"; + + display-timings { + timing@0 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <2>; + hback-porch = <2>; + hsync-len = <41>; + vfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + }; + + soc { + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x200>; + resets = <&rcc STM32F7_APB2_RESET(LTDC)>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; + pinctrl-0 = <<dc_pins>; + + status = "okay"; + u-boot,dm-pre-reloc; + }; + }; +}; + +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&fmc { + /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ + bank1: bank@0 { + u-boot,dm-pre-reloc; + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + /* refcount = (64msec/total_row_sdram)*freq - 20 */ + st,sdram-refcount = < 1542 >; + }; +}; + +&pinctrl { + ethernet_mii: mii@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + ltdc_pins: ltdc@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + qspi_pins: qspi@0 { + pins { + pinmux = , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + usart1_pins_a: usart1@0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; +}; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; + +&qspi { + qflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a13", "jedec,spi-nor"; + spi-max-frequency = <108000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + memory-map = <0x90000000 0x1000000>; + reg = <0>; + }; +}; + +&timer5 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index babd37f1c1..d568765170 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -65,62 +65,8 @@ aliases { serial0 = &usart1; - spi0 = &qspi; - mmc0 = &sdio; - /* Aliases for gpios so as to use sequence */ - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; }; - led1 { - compatible = "st,led1"; - led-gpio = <&gpioi 1 0>; - }; - - button1 { - compatible = "st,button1"; - button-gpio = <&gpioi 11 0>; - }; - - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpiok 3 0>; - status = "okay"; - }; - - panel-rgb@0 { - compatible = "simple-panel"; - backlight = <&backlight>; - enable-gpios = <&gpioi 12 0>; - status = "okay"; - - display-timings { - timing@0 { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <2>; - hback-porch = <2>; - hsync-len = <41>; - vfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <1>; - }; - }; - }; }; &clk_hse { @@ -140,115 +86,6 @@ bias-disable; }; }; - - ethernet_mii: mii@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - qspi_pins: qspi@0 { - pins { - pinmux = , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - fmc_pins: fmc@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - - , - , - - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - ltdc_pins: ltdc@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; }; &usart1 { @@ -257,55 +94,6 @@ status = "okay"; }; -&fmc { - pinctrl-0 = <&fmc_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ - bank1: bank@0 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; - /* refcount = (64msec/total_row_sdram)*freq - 20 */ - st,sdram-refcount = < 1542 >; - }; -}; - -&mac { - status = "okay"; - pinctrl-0 = <ðernet_mii>; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - status = "okay"; - - qflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a13", "jedec,spi-nor"; - spi-max-frequency = <108000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - memory-map = <0x90000000 0x1000000>; - reg = <0>; - }; -}; - &sdio { status = "okay"; cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; @@ -315,8 +103,3 @@ bus-width = <4>; max-frequency = <25000000>; }; - -<dc { - status = "okay"; - pinctrl-0 = <<dc_pins>; -}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index afa7832f89..7209864266 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -57,51 +57,15 @@ compatible = "fixed-clock"; clock-frequency = <0>; }; -}; + }; soc { - u-boot,dm-pre-reloc; - mac: ethernet@40028000 { - compatible = "st,stm32-dwmac"; - reg = <0x40028000 0x8000>; - reg-names = "stmmaceth"; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>, - <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>, - <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>; - interrupts = <61>, <62>; - interrupt-names = "macirq", "eth_wake_irq"; - snps,pbl = <8>; - snps,mixed-burst; - dma-ranges; - status = "disabled"; - }; - - fmc: fmc@A0000000 { - compatible = "st,stm32-fmc"; - reg = <0xA0000000 0x1000>; - clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; - u-boot,dm-pre-reloc; - }; - - qspi: quadspi@A0001000 { - compatible = "st,stm32-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - interrupts = <92>; - spi-max-frequency = <108000000>; - clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>; - resets = <&rcc STM32F7_AHB3_RESET(QSPI)>; - status = "disabled"; - }; usart1: serial@40011000 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>; status = "disabled"; - u-boot,dm-pre-reloc; }; pwrcfg: power-config@58024800 { @@ -116,7 +80,6 @@ reg = <0x40023800 0x400>; clocks = <&clk_hse>; st,syscfg = <&pwrcfg>; - u-boot,dm-pre-reloc; }; pinctrl: pin-controller { @@ -124,7 +87,6 @@ #size-cells = <1>; compatible = "st,stm32f746-pinctrl"; ranges = <0 0x40020000 0x3000>; - u-boot,dm-pre-reloc; pins-are-numbered; gpioa: gpio@40020000 { @@ -134,7 +96,6 @@ reg = <0x0 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; st,bank-name = "GPIOA"; - u-boot,dm-pre-reloc; }; gpiob: gpio@40020400 { @@ -144,7 +105,6 @@ reg = <0x400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; st,bank-name = "GPIOB"; - u-boot,dm-pre-reloc; }; @@ -155,7 +115,6 @@ reg = <0x800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; st,bank-name = "GPIOC"; - u-boot,dm-pre-reloc; }; gpiod: gpio@40020c00 { @@ -165,7 +124,6 @@ reg = <0xc00 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; st,bank-name = "GPIOD"; - u-boot,dm-pre-reloc; }; gpioe: gpio@40021000 { @@ -175,7 +133,6 @@ reg = <0x1000 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; st,bank-name = "GPIOE"; - u-boot,dm-pre-reloc; }; gpiof: gpio@40021400 { @@ -185,7 +142,6 @@ reg = <0x1400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; st,bank-name = "GPIOF"; - u-boot,dm-pre-reloc; }; gpiog: gpio@40021800 { @@ -195,7 +151,6 @@ reg = <0x1800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; st,bank-name = "GPIOG"; - u-boot,dm-pre-reloc; }; gpioh: gpio@40021c00 { @@ -205,7 +160,6 @@ reg = <0x1c00 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; st,bank-name = "GPIOH"; - u-boot,dm-pre-reloc; }; gpioi: gpio@40022000 { @@ -215,7 +169,6 @@ reg = <0x2000 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; st,bank-name = "GPIOI"; - u-boot,dm-pre-reloc; }; gpioj: gpio@40022400 { @@ -225,7 +178,6 @@ reg = <0x2400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; st,bank-name = "GPIOJ"; - u-boot,dm-pre-reloc; }; gpiok: gpio@40022800 { @@ -235,7 +187,6 @@ reg = <0x2800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; st,bank-name = "GPIOK"; - u-boot,dm-pre-reloc; }; sdio_pins: sdio_pins@0 { @@ -331,15 +282,6 @@ interrupts = <50>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; - - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - resets = <&rcc STM32F7_APB2_RESET(LTDC)>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; - u-boot,dm-pre-reloc; - status = "disabled"; - }; }; }; diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi new file mode 100644 index 0000000000..217c937b23 --- /dev/null +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +/{ + chosen { + bootargs = "root=/dev/ram rdinit=/linuxrc"; + }; + + aliases { + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + mmc0 = &sdio2; + spi0 = &qspi; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioa 0 0>; + }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpioj 5 0>; + }; +}; + +&fmc { + /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ + bank1: bank@0 { + u-boot,dm-pre-reloc; + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + /* refcount = (64msec/total_row_sdram)*freq - 20 */ + st,sdram-refcount = < 1542 >; + }; +}; + +&pinctrl { + ethernet_mii: mii@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + qspi_pins: qspi@0 { + pins { + pinmux = , + , + , + , + , + ; + slew-rate = <2>; + }; + }; +}; + +&qspi { + flash0: mx66l51235l { + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <108000000>; + spi-rx-bus-width = <4>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index a23d02d300..046bb225a6 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -50,7 +50,6 @@ compatible = "st,stm32f769-disco", "st,stm32f7"; chosen { - bootargs = "root=/dev/ram rdinit=/linuxrc"; stdout-path = "serial0:115200n8"; }; @@ -60,30 +59,6 @@ aliases { serial0 = &usart1; - spi0 = &qspi; - mmc0 = &sdio2; - /* Aliases for gpios so as to use sequence */ - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; - }; - - led1 { - compatible = "st,led1"; - led-gpio = <&gpioj 5 0>; - }; - - button1 { - compatible = "st,button1"; - button-gpio = <&gpioa 0 0>; }; }; @@ -105,99 +80,6 @@ }; }; - ethernet_mii: mii@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - qspi_pins: qspi@0 { - pins { - pinmux = , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - fmc_pins: fmc@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - - , - , - - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; }; &usart1 { @@ -206,55 +88,6 @@ status = "okay"; }; -&fmc { - pinctrl-0 = <&fmc_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ - bank1: bank@0 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; - /* refcount = (64msec/total_row_sdram)*freq - 20 */ - st,sdram-refcount = < 1542 >; - }; -}; - -&mac { - status = "okay"; - pinctrl-0 = <ðernet_mii>; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - status = "okay"; - - qflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a13", "jedec,spi-nor"; - spi-max-frequency = <108000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - memory-map = <0x90000000 0x1000000>; - reg = <0>; - }; -}; - &sdio2 { status = "okay"; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; -- 2.39.5