Chee Hong Ang [Tue, 12 Feb 2019 08:27:02 +0000 (00:27 -0800)]
ARMv8: Allow SiP service extensions on top of PSCI code
Allow PSCI layer to handle any SiP service functions added by
platform vendors. PSCI layer will look for SiP service function
in the SiP function table located in '._secure_svc_tbl_entries'
section if the SMC function identifier is not found in the PSCI
standard functions table. Use DECLARE_SECURE_SVC macro to declare
and add platform specific SiP service function.
This new section '._secure_svc_tbl_entries' is located next to
'._secure.text' section. Refer to arch/arm/cpu/armv8/u-boot.lds.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Tien Fong Chee [Thu, 31 Jan 2019 11:34:13 +0000 (19:34 +0800)]
misc: fs_loader: Add support for initializing block device
Firmware loader would encounter problem if the block device is accessed
before initializing it. This patch would adding the support of probing
block device and initializing block before the block device is accessed by
firmware loader.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Philippe Reynes [Fri, 15 Mar 2019 14:14:34 +0000 (15:14 +0100)]
include: linux: io: define devm_ioremap on board with ioremap
The macro devm_ioremap is only defined for configuration
that doesn't have ioremap. But this macro may also be
defined on configuration with ioremap.
This patch remove the condition for the macro devm_ioremap,
so it's always defined.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Boris Brezillon [Fri, 15 Mar 2019 14:14:32 +0000 (15:14 +0100)]
mtd: nand: provide several helpers to do common NAND operations
Linux commit 97d90da8a88 ("mtd: nand: provide several helpers
to do common NAND operations")
This is part of the process of removing direct calls to ->cmdfunc()
outside of the core in order to introduce a better interface to execute
NAND operations.
Here we provide several helpers and make use of them to remove all
direct calls to ->cmdfunc(). This way, we can easily modify those
helpers to make use of the new ->exec_op() interface when available.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[miquel.raynal@free-electrons.com: rebased and fixed some conflicts] Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[Philippe Reynes: adapt code to u-boot and only keep new function]
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Marc Gonzalez [Fri, 15 Mar 2019 14:14:31 +0000 (15:14 +0100)]
mtd: nand: import nand_hw_control_init()
Linux commit d45bc58dd3b ("mtd: nand: import nand_hw_control_init()")
The code to initialize a struct nand_hw_control is duplicated across
several drivers. Factorize it using an inline function.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Philippe Reynes: adapt code to u-boot and only keep new function]
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Brian Norris [Fri, 15 Mar 2019 14:14:30 +0000 (15:14 +0100)]
mtd: add get/set of_node/flash_node helpers
Linux commit 28b8b26b308 ("mtd: add get/set of_node/flash_node helpers")
We are going to begin using the mtd->dev.of_node field for MTD device
nodes, so let's add helpers for it. Also, we'll be making some
conversions on spi_nor (and nand_chip eventually) too, so get that ready
with their own helpers.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Philippe Reynes: only add function nand_set_flash_node and
nand_get_flash_node because others were already backported]
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
This fixes a disconnect issue detected with fastboot command, when using
dwc2 driver.
- On u-boot side:
uboot>$ fastboot 0
- On USB host PC side, few seconds after
PC>$ fastboot reboot # Get stuck, uboot target never reboots
By enabling DEBUG_ISR logs, the bus suspend interrupt is seen before the
PC command has been issued. When the USB bus suspend occurs, there's a HACK
that disables the fastboot (composite driver). Here is the call stack
upon USB bus suspend:
- dwc2_handle_usb_suspend_intr()
- dev->driver->disconnect()
- composite_disconnect()
- reset_config()
- f->disable()
- fastboot_disable()
- usb_ep_disable(f_fb->out_ep);
- usb_ep_disable(f_fb->in_ep);
.. other disable calls.
When the resume interrupt happens, everything has been disabled, then
nothing happens. fastboot command gets stuck on HOST side.
Remove original HACK, that disconnects the composite driver upon
USB bus suspend. Implement disconnect detection instead:
- check GINTSTS OTG interrupt
- read GOTGINT register
- check GOTGINT, SesEndDet bit (e.g. session end)
This is inspired by what is implemented currently in Linux dwc2 driver.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Marek Vasut <marex@denx.de>
Our R-Car3 Android userspace relies on the output of 'fastboot
getvar platform' and U-Boot currently is not able to handle it:
host $> fastboot getvar platform
getvar:platform FAILED (remote: Variable not implemented)
finished. total time: 0.001s
We either have the option of adding 'fastboot.platform' variable
to the default/saved environment as a workaround or add proper
'fastboot getvar platform' support in U-Boot via this patch.
In the latter case, other platforms can benefit from it too.
Note that R-Car3 already exports 'platform' environment variable via
v2019.01 commit 00e4b57e9e71c3 ("ARM: rmobile: Set environment variable
containing CPU type").
Patrick Delaunay [Fri, 29 Mar 2019 14:42:24 +0000 (15:42 +0100)]
stm32mp1: add stusb1600 support for DK1 and DK2 board
The DK1 and DK2 boards use the USB Type-C controller STUSB1600.
This patch updates:
- the device tree to add the I2C node in the DT
- the board stm32mp1 to probe this I2C device and use this controller
to check cable detection.
- the DWC2 driver to support a new dt property
"u-boot,force-b-session-valid" which forces B session and
device mode; it is a workaround because the VBUS sensing and
ID detection isn't available with stusb1600.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Patrick Delaunay [Fri, 29 Mar 2019 14:42:22 +0000 (15:42 +0100)]
stm32mp1: remove CONFIG_USB_DWC2, HOST support for USBO
Remove the HOST support for STM32MP1 USBO device = OTG DWC2.
The current DWC2 driver have no dynamic detection of device,
So it is dangerous to have start 3V3 when PC is
connected to the micro USB connector.
=> it is preferable to have only DEVICE support
CONFIG_USB_GADGET_DWC2_OTG for OTG port
See DWC3 driver for clean dual role support...
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrice Chotard [Fri, 29 Mar 2019 14:42:20 +0000 (15:42 +0100)]
usb: dwc2_udc_otg: Add tx_fifo_sz array support
All TX fifo size can be different, add tx_fifo_sz_array[]
into dwc2_plat_otg_data to be able to set them.
tx_fifo_sz_array[] is 17 Bytes long and can contains max 16
tx fifo size (synopsys IP supports max 16 IN endpoints).
First entry of tx_fifo_sz_array[] is the number of valid
fifo size the array contains.
In case of tx_fifo_sz_array[] doesn't contains the same
number of element than max hardware endpoint, display
a warning message.
Compatibility with board which doesn't use tx_fifo_sz_array[]
(Rockchip rk322x/rk3128/rv1108/rk3288/rk3036) is kept.
Patrick Delaunay [Fri, 29 Mar 2019 14:42:19 +0000 (15:42 +0100)]
usb: dwc2_udc_otg: Read MAX_HW_ENDPOINT from HWCFG4 register
Some DWC2 ip variant doesn't use 16 hardware endpoint as hardcoded
in the driver. Bits INEps [29:26] of HWCFG4 register allows to get
this information.
Eugeniu Rosca [Tue, 26 Mar 2019 16:46:14 +0000 (17:46 +0100)]
fastboot: getvar: correct/rename "has_slot" to "has-slot"
Since its inception in upstream fastboot android-n-preview-1 [1],
"has-slot" option has never taken the form of "has_slot". Amongst the
users of "getvar has-slot:" is the upstream bootloadertest.py [2].
Current U-Boot "has_slot" version must be a typo. Fix it.
More serious, that comes under same circumstances, is a compilation error due
to absence of macro parameter:
In file included from include/image.h:45,
from include/common.h:35,
from cmd/dfu.c:13:
include/command.h:207:24: error: expected expression before ‘,’ token
# define _CMD_HELP(x) x,
^
include/command.h:286:18: note: in expansion of macro ‘_CMD_HELP’
_cmd, _usage, _CMD_HELP(_help) _CMD_COMPLETE(_comp) }
^~~~~~~~~
include/command.h:290:3: note: in expansion of macro ‘U_BOOT_CMD_MKENT_COMPLETE’
U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
^~~~~~~~~~~~~~~~~~~~~~~~~
include/command.h:332:2: note: in expansion of macro ‘U_BOOT_CMD_COMPLETE’
U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, NULL)
^~~~~~~~~~~~~~~~~~~
cmd/dfu.c:70:1: note: in expansion of macro ‘U_BOOT_CMD’
U_BOOT_CMD(dfu, CONFIG_SYS_MAXARGS, 1, do_dfu,
^~~~~~~~~~
make[1]: *** [scripts/Makefile.build:279: cmd/dfu.o] Error 1
make: *** [Makefile:1518: cmd] Error 2
Put empty string unconditionally to have macro parameter present.
Fixes: 0f44d33536a5 ("dfu: Fix up the Kconfig mess") Cc: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Lukasz Majewski <lukma@denx.de>
Alex Kiernan [Thu, 18 Apr 2019 11:10:50 +0000 (11:10 +0000)]
usb: Select USB_MUSB_DSPS with USB_MUSB_TI
USB_MUSB_TI requires USB_MUSB_DSPS, failing at link time if it's not
selected:
drivers/usb/musb-new/built-in.o: In function `ti_musb_host_ofdata_to_platdata':
drivers/usb/musb-new/ti-musb.c:193: undefined reference to `musb_dsps_ops'
or if OF_CONTROL is not selected:
arch/arm/mach-omap2/built-in.o:(.data.usb0+0x24): undefined reference to `musb_dsps_ops'
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at> Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Marek Vasut [Wed, 10 Apr 2019 11:44:05 +0000 (13:44 +0200)]
timer: dw-apb: Add missing 64bit up-conversion
The generic timer count is an incrementing 64bit value and a timer driver
must return an incrementing 64bit value. The DW APB timer only provides a
32bit timer counting down, thus the result must be inverted and converted
to a 64bit value. The current implementation is however missing the 64bit
up-conversion and this results in random timer roll-overs, which in turn
triggers random timeouts throughout the codebase.
This patch adds the missing 64bit up-conversion to fix the issue.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Merge qspi dts node from Linux.
Commit 0cb140d07fc75fb (arm64: dts: stratix10: Add QSPI support for Stratix10)
Add -u-boot.dtsi files for non Linux dts properties and
update properties for Uboot.
- add u-boot,dm-pre-reloc
- add alias for spi0
- change compatible for flash
- support quad read and quad write
- change maximum frequency to 100MHz
Tested on Stratix 10 SoC devkit.
SOCFPGA_STRATIX10 # sf probe 0:0
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Ley Foon Tan [Thu, 21 Mar 2019 17:24:05 +0000 (01:24 +0800)]
ddr: altera: Stratix10: Add ECC memory scrubbing
Scrub memory content if ECC is enabled and it is not
from warm reset boot.
Enable icache and dcache before scrub memory
and use "DC ZVA" instruction to clear memory
to zeros. This instruction writes a cache line
at a time and it can prevent false ECC error
trigger if write cache line partially.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
The stratix10 socdk ships with 4GB of memory. Modify the
device tree to represent this. Note that to access 4GB of
memory in Stratix 10, due to the IO space from 2GB to 4GB,
we use the fact that the DDR controller ignores upper address
bits outside of the configured DRAM's size. This means that
, the 4GB DRAM is mapped to memory every 4GB.
For an 8GB memory, you can either live with the 2GB IO space,
and loose access to that memory from the processor, or use
the same trick:
Ley Foon Tan [Thu, 21 Mar 2019 17:24:01 +0000 (01:24 +0800)]
ddr: altera: Stratix10: Add multi-banks DRAM size check
Stratix 10 maps dram from 0 to 128GB. There is a 2GB hole
in the memory for peripherals and other IO from 2GB to 4GB.
However the dram controller ignores upper address bits for
smaller dram configurations. Example: a 4GB dram
maps to multiple locations, every 4GB on the address.
Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.
This gets us rid of one ad-hoc call to socfpga_per_reset().
The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.
SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
reset: socfpga: add reset handling for old kernels
This adds code to take peripherals out of reset based on an environment
variable. This is in preparation for removing the code that does this from
SPL.
However, some drivers even in current Linux cannot handle peripheral reset,
so until this works, we need a compatibility workaround.
This workaround is implemented in the 'assert' and 'remove' callbacks of
this reset driver: the 'assert' callback does not disable peripherals that
were already taken out of reset, while the 'remove' callback, which is
called on OS_PREPARE, deasserts all peripheral resets if the environment
variable "socfpga_legacy_reset_compat" is set to 1, which is what the gen5
SPL did up to now.
This is in preparation to clean up the SPL and implementing proper reset
handling for U-Boot.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
arm: socfpga: gen5: deassert peripheral reset by default
To keep the current behaviour of taking all peripherals out of reset
before booting the OS before removing that code from socfpga gen5 SPL,
this enables the new behaviour by default for all gen5 boards by adding
the environment variable "socfpga_legacy_reset_compat=1" to the default
environment.
This can be overridden in board config files or by saving an environment
without this variable enabled.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The only member of this driver's priv struct is a pointer, which is
called 'membase'. However, since this driver handles multiple sub-
architectures, this is not the base address from dts but the base
address of some common registers of those sub-arches.
Reflect this better in sourcecode by renaming 'membase' to 'modrst_base'.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The SPL for socfpga gen5 currently takes all peripherals out of reset
unconditionally. To implement proper reset handling for peripherals,
the reset node has to be provided with the SPL dts.
In preparation to move the DDR driver to DM, the sdr node is required
in SPL, too.
This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon
files so that the reset manager and SDR driver correctly probe in SPL.
It centralizes these settings into a common file since in contrast to
boot-type specific nodes, "soc", "rst" and "sdr" are always needed.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This is again a sync to linux-next + pending patches in Dinh's tree at
commit 1c909b2dfe6a ("ARM: dts: socfpga: update more missing reset
properties")'
It adds missing peripheral reset properties to socfpga.dtsi and removes
U-Boot specific leftovers from socfpga_cyclone5_socrates.dts.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
arm64:
- Add support for zc39dr decoding
- Disable WDT for zcu100
- Small changes in reset_reason()
- Some DT changes (spi)
- Tune qspi-mini configuration
- Remove useless eeprom setting
- Fix two sdhci boot case
Andre Przywara [Fri, 12 Apr 2019 10:58:54 +0000 (16:28 +0530)]
sunxi: update SATA driver to always use DM_SCSI
It seems like the Allwinner SATA driver is already quite capable of
using the driver model, so we can force this on all boards and can
remove support for a non-DM_SCSI build.
This removes the warning about boards with SATA ports not being
DM_SCSI compliant.
It also takes the opportunity to move the driver out of the board/sunxi
directory to join its siblings in drivers/ata, and to make it a proper
Kconfig citizen.
The board defconfigs stay untouched.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: select DM_SCSI separately] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
- s/uart0_pins_a/uart0_pb_pins for
sun7i-a20-ainol-aw1.dts
sun7i-a20-m5.dts
sun7i-a20-primo73.dts
sun7i-a20-yones-toptech-bd1078.dts
sunxi-itead-core-common.dtsi
- s/gmac_pins_mii_a/gmac_rgmii_pins for
sun7i-a20-m5.dts
- drop i2c0, i2c1 pins from
sunxi-itead-core-common.dtsi
- drop mmc0 pins from
sun7i-a20-primo73.dts
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Tue, 9 Apr 2019 09:38:51 +0000 (15:08 +0530)]
arm: allwinner: r40: Sync R40 dts(i) files from Linux 5.1-rc2
Sync sun8i-r40 dts(i) files from Linux 5.1-rc2
Linux commit details about the sun8i-r40* sync:
"ARM: dts: sun8i: r40: bananapi-m2-ultra: Add Bluetooth device node"
(sha1: 1e5f1db4ccd8348a21da55bff82f4263000879ef)
Jagan Teki [Wed, 27 Feb 2019 18:56:51 +0000 (00:26 +0530)]
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle
Unlike other Allwinner SoC's R40 GMAC clock control register
is locate in CCU, but rest located via syscon itself. Since
the phandle property for current code look for 'syscon' and
it will grab the respective ccu or syscon base address based
on DT property defined in respective SoC dtsi.
So, use the existing 'syscon' code even for R40 for retrieving
GMAC clock via CCU and update the register directly in
sun8i_emac_set_syscon instead of writing it separately using
ccm base.
Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 15 Apr 2019 11:12:16 +0000 (16:42 +0530)]
clk: sunxi: r40: Fix GMAC reset reg offset
GMAC reset reg offset added by below commit seems to assume
it as EMAC but R40 indeed using GMAC.
"clk: sunxi: Implement EMAC, GMAC clocks, resets"
(sha1: 68620c9698f109c1f001f80d282138a5c67cabef)
So, fix by updating the reg offset for RST_BUS_GMAC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
arm64: zynqmp: fix preprocessor check for SPL_ZYNQMP_TWO_SDHCI
A missing CONFIG_ prefix while checking for this Kconfig variable makes the
check always fail. Fix it. While there also switch from the '#if defined'
form to the '#ifdef' form as the other checks in this function.
Fixes: 35e2b92344b1 ("arm64: zynqmp: Fix logic around CONFIG_ZYNQ_SDHCI") Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
projects / u-boot.git / log