Patrick Delaunay [Mon, 10 Jul 2023 08:44:10 +0000 (10:44 +0200)]
ARM: dts: stm32mp13: remove shmem for scmi-optee
CFG_STM32MP1_SCMI_SHM_SYSRAM will be disabled by default for STM32MP13x
SoCs in next OP-TEE version and the OP-TEE SMCI server uses the OP-TEE
native shared memory registered by clients.
To be compatible by default with this configuration this patch removes
the shared memory in the SCMI configuration and the associated reserved
memory in SRAM.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Mon, 10 Jul 2023 08:44:09 +0000 (10:44 +0200)]
ARM: dts: stm32mp15: remove shmem for scmi-optee
Since OP-TEE commit 89ba3422ee80 ("plat-stm32mp1: scmi_server: default
use OP-TEE shared memory"), integrated in OP-TEE 3.22.0-rc1
the default configuration for STM32MP15x SoCs changes,
CFG_STM32MP1_SCMI_SHM_SYSRAM is disabled by default and the OP-TEE SMCI
server uses ithe OP-TEE native shared memory registered by clients.
To be compatible by default with this configuration and the next OP-TEE
version, this patch removes the SHMEM in the SCMI configuration and the
associated reserved memory in the last 4KByte page of SRAM,
in the STM32MP15 device tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tim Harvey [Thu, 13 Jul 2023 18:56:07 +0000 (11:56 -0700)]
phy: phy-imx8mq-usb: add vbus regulator support
Add support for enabling and disabling vbus-supply regulator found
on several imx8mp boards in the usb3_phy0 and usb3_phy1 nodes.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
usb: dwc3: Fix remove function if there is no ulpi_reset gpio
As ulpi_reset gpio is now optional, we need to check it when doing
the 'dwc3_generic_remove' function. Check if it is declared before
accessing the ulpi_reset.
Fixes: 237d1f60b1d ("usb: dwc3: Use the devm_gpiod_get_optional()
API for reset gpio")
Reported-by: Thomas Nizan <tnizan@witekio.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Tom Rini [Wed, 23 Aug 2023 15:03:46 +0000 (11:03 -0400)]
Merge tag 'doc-2023-10-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for doc-2023-10-rc4
Documentation:
* Fix documentation for TI boards
* Describe running on VirtualBox
* List build dependencies for building documenation
* Add references to U-Boot talks
Other:
* Fix error handling in the setexpr command (printf_str)
Documentation extended with specific information for VirtualBox
The configuration for EFI is enhanced to start U-Boot at VirtualBox (x86_64)
with all features like booting with help of boot scripts and extended linux.
This documentation describes how to use U-Boot at VirtualBox to boot
Linux systems with a some simple example.
Signed-off-by: Thomas Mittelstaedt <thomas.mittelstaedt@de.bosch.com>
doc: board: ti: k3: Fix up OpenOCD references and debug info
Fix minor path and config macro name updates to sync with latest
OpenOCD and U-Boot configurations.
Fixes: effe50854a69 ("doc: board: ti: k3: Add a guide to debugging with OpenOCD") Signed-off-by: Jonathan Humphreys <j-humphreys@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Nishanth Menon [Tue, 22 Aug 2023 16:41:01 +0000 (11:41 -0500)]
doc: board: ti: j721e: provide image alt text
Provide alternative text for image.
Fixes: 3b83dff183b5 ("doc: board: ti: j721e: Convert the image format to svg") Reported-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Nishanth Menon <nm@ti.com>
Nishanth Menon [Tue, 22 Aug 2023 16:41:00 +0000 (11:41 -0500)]
doc: board: ti: j7200: provide image alt text
Provide alternative text for image.
Fixes: f4ade09a1e76 ("doc: board: ti: j7200: Convert the image format to svg") Reported-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Nishanth Menon <nm@ti.com>
Fixes: 34f76921d801 ("doc: board: ti: am62x: Convert the image format to svg") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Nishanth Menon <nm@ti.com>
Chanho Park [Fri, 18 Aug 2023 05:11:03 +0000 (14:11 +0900)]
riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback
Since the Patch 55171aedda88, VisionFive2 booting has been broken [1].
VisionFive2 board requires to enable CONFIG_TIMER_EARLY but booting went
to panic from initr_dm_devices due to lack of a timer device.
Thus, we need to move riscv_cpu_probe function in order to register
the timer earlier than initr_dm_devices.
Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Tested-by: Milan P. Stanić <mps@arvanta.net> Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev> Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
Chanho Park [Fri, 18 Aug 2023 05:11:02 +0000 (14:11 +0900)]
dm: event: add EVT_DM_POST_INIT_R event type
This patch introduces EVT_DM_POST_INIT_R event type for handling hooks
after relocation.
Fixes: 55171aedda88 ("dm: Emit the arch_cpu_init_dm() even only before relocation") Suggested-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Tested-by: Milan P. Stanić <mps@arvanta.net> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev> Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
Fixed missing event name in event.c: Signed-off-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Sun, 13 Aug 2023 19:52:19 +0000 (21:52 +0200)]
test: cpu: Handle both 32bit and 64bit CPUs
Handle both 32bit and 64bit systems, i.e. sandbox and sandbox64
the same way drivers/cpu/cpu_sandbox.c does, that is in case
CONFIG_PHYS_64BIT is enabled, assume 64bit address width, else
assume 32bit address width. This fixes ut_dm_dm_test_cpu test
failure on sandbox64.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Sun, 13 Aug 2023 05:15:05 +0000 (07:15 +0200)]
configs: sandbox64: Enable video 16bpp and 24bpp support
Align the sandbox64 defconfig with sandbox defconfig. Enable missing
16bpp and 24bpp video support. This fixes ut_dm_dm_test_video_bmp16
and ut_dm_dm_test_video_bmp24 tests .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Sun, 13 Aug 2023 03:32:08 +0000 (05:32 +0200)]
test: dm: pinmux: Handle %pa in pinctrl-single mux output
The pinctrl-single driver uses %pa to print register value
in its single_get_pin_muxing() output. Handle this properly
in the test based on CONFIG_PHYS_64BIT .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Paul Barker [Fri, 18 Aug 2023 13:17:21 +0000 (14:17 +0100)]
arm: rmobile: Fix off-by-one error in cpuinfo
In rmobile_cpuinfo_idx() there is an off-by-one error in accessing the
rmobile_cpuinfo array.
At the end of the loop, i is equal to the array size, i.e.
rmobile_cpuinfo[i] accesses one entry past the end of the array. The
last entry in the array is a fallback value so the loop should count to
ARRAY_SIZE(rmobile_cpuinfo) - 1 instead, this will leave i equal to the
index of the fallback value if no match is found.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tom Rini [Sat, 19 Aug 2023 14:13:28 +0000 (10:13 -0400)]
Merge tag 'doc-2023-10-rc3-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2023-10-rc3-2
Documentation:
* csf_examples: csf.sh: Remove unneeded export ATF_LOAD_ADDR line
* printf() codes: correct format specifier for unsigned int
* Fix typos in clk.h, irq.h.
* Correct description of proftool
Other:
* Quieten test for erofs filesystem presence
* spl: don't assume NVMe partition 1 exists
Fabio Estevam [Tue, 15 Aug 2023 13:48:01 +0000 (10:48 -0300)]
doc: csf_examples: csf.sh: Remove unneeded export ATF_LOAD_ADDR line
Originally, exporting the ATF_LOAD_ADDR was required, but since binman has
been used to generate the flash.bin, it is no longer needed to do
such manual export.
There is no requirement that a partition 1 exists in a partition table.
We should not try to retrieve information about it.
We should not even try reading with partition number
CONFIG_SYS_NVME_BOOT_PARTITION here as this is done in the fs_set_blk_dev()
call anyway.
Fixes: 8ce6a2e17577 ("spl: blk: Support loading images from fs") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Jonas Karlman [Thu, 17 Aug 2023 21:52:48 +0000 (21:52 +0000)]
rockchip: rk3566-anbernic-rgxx3: Rename defconfig to include SoC name
Rename defconfig to include SoC name, use similar pattern as other
RK356x boards: <soc>-<name>.dts -> <name>-<soc>_defconfig
Suggested-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Fri, 18 Aug 2023 14:05:04 +0000 (10:05 -0400)]
Merge tag 'tegra-for-2023.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-tegra
ARM: tegra: Changes for v2023.10-rc1
This adds support for various new Tegra30 boards (ASUS, LG and HTC) and
has some other minor enhancements, such as enabling the poweroff command
on several Tegra210 and Tegra186 boards.
Jonas Karlman [Thu, 17 Aug 2023 06:04:34 +0000 (06:04 +0000)]
doc: rockchip: Add supported RK3566/RK3568 boards
Update Rockchip documentation to include RK3566/RK3568 boards already
supported. Also list Pine64 boards under RK3566 and drop defconfig to
match other listed boards.
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 7 Aug 2023 21:08:11 +0000 (17:08 -0400)]
arm: Add arch/arm/dts/Makefile specifically to MAINTAINERS
In order to reduce the number of people that are cc'd on a patch for
simply touching arch/arm/dts/Makefile (which is a big common file) add
an entry specifically to MAINTAINERS under the ARM entry.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 16 Aug 2023 15:23:58 +0000 (11:23 -0400)]
Merge tag 'u-boot-stm32-20230816' of https://source.denx.de/u-boot/custodians/u-boot-stm
DHSOM: Power cycle Buck3 in reset
DHCOM: Switch DWMAC RMII clock to MCO2
stm32f746: fix display pinmux
stm32mp: psci: Inhibit PDDS because CSTBYDIS is set
stm32mp1: DT alignment with v6.4
stm32mp1: add splashscreen with STMicroelectronics logo
stm32mp1: clk: remove error for disabled clock in stm32mp1_clk_get_parent
serial: stm32: Extend TC timeout
Marek Vasut [Wed, 26 Jul 2023 23:58:07 +0000 (01:58 +0200)]
ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM
The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC
block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK
pad for the PHY and the same 50 MHz clock are fed back to ETHRX via
internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at
all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and
the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad
using external pad-to-pad connection.
Option (1) has two downsides. ETHCK_K is supplied directly from either
PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and
since the same PLL output is also used to supply SDMMC blocks, the
performance of SD and eMMC access is affected. The second downside is
that using this option, the EMI of the SoM is higher.
Option (2) solves both of those problems, so implement it here. In this
case, the PLL4_P is no longer limited and can be operated faster, at
100 MHz, which improves SDMMC performance (read performance is improved
from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M
count=1). The EMI interference also decreases.
Ported from Linux kernel commit 73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM")
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Thu, 6 Jul 2023 21:32:27 +0000 (23:32 +0200)]
ARM: stm32: Inhibit PDDS because CSTBYDIS is set
The PWR_MPUCR CSTBYDIS bit is set, therefore the CA cores can never
enter CStandby state and would always end up in CStop state. Clear
the PDDS bit, which indicates the CA cores can enter CStandby state
as it makes little sense to keep it set with CSTBYDIS also set.
This does however fix a problem too. When both PWR_MPUCR and PWR_MCUCR
PDDS bits are set, then the chip enters CStandby state even though the
PWR_MCUCR CSTBYDIS is set. Clearing the PWR_MPUCR PDDS prevents that
from happening.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrick Delaunay [Fri, 23 Jun 2023 13:05:16 +0000 (15:05 +0200)]
clk: stm32mp1: remove error for disabled clock in stm32mp1_clk_get_parent
To disabled a clock in clock tree initialization for a mux of STM32MP15,
the selected clock source index is set with the latest possible index for
the number of bit used. Today this valid configuration cause a error
in U-Boot messages, for example with CLK_ETH_DISABLED, when this clock
is not needed for the used ETH PHY without crystal:
no parents defined for clk id 123
This patch change the level of this message to avoid this trace for
valid clock tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Wed, 17 May 2023 22:02:39 +0000 (00:02 +0200)]
ARM: stm32: Power cycle Buck3 in reset on DHSOM
In case the DHSOM is in suspend state and either reset button is pushed
or IWDG2 triggers a watchdog reset, then DRAM initialization could fail
as follows:
Avoid this failure by not keeping any Buck regulators enabled during reset,
let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3
VDD enabled during reset is ST specific, move this addition to ST specific
SPL board initialization so that it wouldn't affect the DHSOM .
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tom Rini [Tue, 15 Aug 2023 17:08:17 +0000 (13:08 -0400)]
Merge tag 'efi-2023-10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2023-10-rc3
Documentation:
* Correct description of board_get_usable_ram_top
* Add partition API to HTML documentation
* Describe lmb_is_reserved
* doc/sphinx/requirements.txt: Bump certifi up
UEFI:
* Fix efi_add_known_memory
* Make distro_efi_boot() static
board_get_usable_ram_top() returns a physical address that is stored in
gd->ram_top. The return type of the function should be phys_addr_t like the
current type of gd->ram_top.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
In efi_add_known_memory() we currently call board_get_usable_ram_top() with
an incorrect value 0 of parameter total_size. This leads to an incorrect
value for ram_top depending on the code in board_get_usable_ram_top().
Use the value of gd->ram_top instead which is set before relocation by
calling board_get_usable_ram_top().
Fixes: 7b78d6438a2b ("efi_loader: Reserve unaccessible memory") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Bin Meng [Thu, 3 Aug 2023 09:30:05 +0000 (17:30 +0800)]
bootmeth: efi: Make distro_efi_boot() static
As it is only called in bootmeth_efi.c
Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Sam Edwards [Tue, 25 Jul 2023 22:13:05 +0000 (16:13 -0600)]
i2c: mvtwsi: reset controller if stuck in "bus error" state
The MVTWSI controller can act either as a master or slave device. When
acting as a master, the FSM is driven by the CPU. As a slave, the FSM is
driven by the bus directly. In what is (apparently) a safety mechanism,
if the bus transitions our FSM in any improper way, the FSM goes to a
"bus error" state (0x00). I could find no documented or experimental way
to get the FSM out of this state, except for a controller reset.
Since U-Boot only uses the MVTWSI controller as a bus master, this
feature only gets in the way: we do not care what happened on the bus
previously as long as the bus is ready for a new transaction. So, when
trying to start a new transaction, check for this state and reset the
controller if necessary.
Note that this should not be confused with the "deblocking" technique
(used by the `i2c reset` command), which involves pulsing SCL repeatedly
if SDA is found to be held low, in an attempt to force the bus back to
an idle state. This patch only resets the controller in case something
else had previously upset it, and (in principle) results in no
externally-observable change in behavior.
Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
Jonas Karlman [Mon, 14 Aug 2023 00:28:26 +0000 (00:28 +0000)]
pinctrl: rockchip: Fix drive and input schmitt on RK3568
On RK3568 most pins have a configurable drive strength of level 0-5 and
some pins level 0-11. When rk3568_set_drive is called with a strength
value above 7 the drv value written to reg may overflow into the write
enable bits, resulting in a bad configuration.
This cause e.g. ethernet PHY on Radxa CM3-IO board not to work after
drive is configured according to the device tree.
Level 6-11 can be configured using a second reg for some pins, however
the drv value is reused resulting in lower 6 bits being written to reg.
Input schmitt is configured in 2-bit fields on RK3568 compared to
earlier generation and 2'b10 should be used to enable input schmitt.
Change to use regmap_update_bits with a rmask to fix the overflow issue
and closer match the linux driver. Bit shift the drv value used for the
second reg to configure drive strength level 6-11. Also write correct
values for input schmitt setting.
Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Meng Li [Wed, 26 Jul 2023 02:42:35 +0000 (10:42 +0800)]
rpi: set the correct parameter for simple framebuffer node
When raspberrpi-4b platform boots up, there are 2 sets of same bootup
log displayed on HDMI monitor screen, it looks like the screen is split
into 2 parts. The root cause is that video format of u-boot is different
from kernel. The fixing "a8r8g8b8" video format is used in u-boot, but
"r5g6b5" video format from framebuffer node is used in kernel image. In
order to avoid weird display status on screen, it needs to set the correct
parameter for simple framebuffer node even if it has existed.
Jason Wessel [Wed, 26 Jul 2023 02:42:34 +0000 (10:42 +0800)]
bcm2835: Add simiple-framebuffer for use with fkms
When the fkms dtb overlay is used only the simple-framebuffer is
presented as a usable video display. So, add "simple-framebuffer"
compatible to enable video driver bcm2835.
Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Meng Li <Meng.Li@windriver.com>
Bin Meng [Thu, 3 Aug 2023 09:32:41 +0000 (17:32 +0800)]
video: vidconsole: Fix null dereference of ops->measure
At present vidconsole_measure() tests ops->select_font before calling
ops->measure, which would result in a null dereference when the console
driver provides no ops for measure.
Fixes: b828ed7d7929 ("console: Allow measuring the bounding box of text") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Hai Pham [Mon, 19 Jun 2023 22:43:18 +0000 (00:43 +0200)]
ARM: rmobile: Update little‐endian byte order option in srec_cat command
Since srecord v1.60, option "-Little_Endian_CONSTant" is deprecated.
Fix the build warnings by updating little‐endian byte order option in
srec_cat command when generating loader header.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Sat, 25 Apr 2020 12:57:55 +0000 (14:57 +0200)]
clk: renesas: Tear clock controller down last before booting OS
Once all the other drivers got torn down in preparation for the OS
to start, tear down the clock controller last. The clock controller
must be torn down last as some of the clock which get turned off
might have still been needed during the teardown stage of the other
drivers.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Massimo Pegorer [Thu, 3 Aug 2023 11:08:13 +0000 (13:08 +0200)]
dts: rockchip: rk3308: Avoid warning for serial probe on prereloc
Make device tree complete and consistent for pre relocation phase. Some
nodes are missing, causing warnings to be issued on serial port probing
during pre relocation phase (uclass_get_device_by_phandle_id fails when
called by pinctrl_select_state_full: none of these failures is fatal
nor causing issues). Add to *-u-boot.dtsi all required nodes with the
'bootph-some-ram' attribute.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Massimo Pegorer [Thu, 3 Aug 2023 11:08:12 +0000 (13:08 +0200)]
clk: rockchip: rk3308: Support reading UART rate and clock registers
Add support to read RK3308 registers used to configure UART clocks, and
thus to get UART rate and baudrate. This fixes clock_get_rate returning
error on serial device probing. Moreover, there is no need anymore to
use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files
for all cases where UART is not inited by U-Boot proper or by SPL o by
TPL code but by a preliminary external boot phase (for Rock PI S, UART
is inited by external TPL).
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Massimo Pegorer [Thu, 3 Aug 2023 11:08:11 +0000 (13:08 +0200)]
clk: rockchip: rk3308: Fix ordering between masking and shifting
As per definitions of masks and shift offsets in cru_rk3308.h, values
read from registers must be first masked and then shifted. By the way,
this fix is binary invariant, because in all of fixed cases the shift
offset is zero.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Massimo Pegorer [Wed, 2 Aug 2023 17:05:24 +0000 (19:05 +0200)]
rockchip: spl: Drop out of scope debug message related to uart init
Debug uart is no more inited in board_init_f function: remove this
debug message from board_init_f. If an earliest-as-possible message
after debug uart initialization is needed, enable DEBUG_UART_ANNOUNCE
Kconfig option, instead.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Massimo Pegorer [Wed, 2 Aug 2023 17:05:23 +0000 (19:05 +0200)]
rockchip: spl: Drop useless call to debug_uart_init
Since commit 0dba45864b2a ("arm: Init the debug UART") function
debug_uart_init is called in crt files _main before calling
board_init_f. Therefore, there is no need to call it again
inside board_init_f implementation in arm/mach-rockchip/spl.c.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 4 Aug 2023 09:34:01 +0000 (09:34 +0000)]
rockchip: rk356x-u-boot: Set max-frequency prop in sdhci node
Most board device trees for RK356x set max-frequency = <200000000> in
the sdhci node, some boards like Quartz64 do not. This result in an
error message due to sdhci driver trying to set a clock rate of 0
instead of the max-frequency value.
rockchip_sdhci_probe clk set rate fail!
Fix this by setting a common max-frequency in rk356x-u-boot.dtsi. A
patch to set default max-frequency of sdhci node in linux is planned.
Also remove the forced status = "okay" for the sdhci and sdmmc0 nodes,
boards already set correct state for these nodes.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 4 Aug 2023 09:34:00 +0000 (09:34 +0000)]
clk: rockchip: rk3568: Add dummy support for GMAC speed clocks
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the
assigned-clocks property of the gmac1 node. This result in a ENOENT
error when driver core tries to set a parent for this clock.
The clock speed in rgmii/rmii mode is changed using clk_set_rate of the
tx_rx clock and not using clk_set_parent of the speed clock.
Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk
driver to allow a driver for gmac node to probe.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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