video: zynqmp: Driver for Xilinx ZynqMP DisplayPort Subsystem
The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort
Subsystem. It includes a buffer manager, blender, an audio mixer and a
DisplayPort source controller (transmitter). The DisplayPort controller can
source data from memory (non-live input) or the stream (live input). The
DisplayPort controller is responsible for managing the link and physical
layer functionality. The controller packs audio/video data into transfer
units and sends them over the main link. The link rate and lane counts can
be selected based on the application bandwidth requirements. The
DisplayPort pipeline consists of the DisplayPort direct memory access (DMA)
for fetching data from memory. The DisplayPort DMA controller (DPDMA)
supports up to six input channels as non-live input.
This driver supports the DisplayPort Subsystem and implements
1)640x480 resolution
2)RGBA8888 32bpp format
3)DPDMA channel 3 for Graphics
4)Non-live input
5)Fixed 5.4G link rate
6)Tested on ZCU102 board
There will be additional work to configure GT lines based on DT, higher
resolutions, support for more compressed video formats, spliting code to
more files, add support for EDID, audio support, using clock framework for
all clocks and in general code clean up.
Michal Simek [Wed, 17 May 2023 08:42:07 +0000 (10:42 +0200)]
video: Add support for RGBA8888 format
Add support for RGBA8888 32bpp format where pixels are picked in
32-bit integers, where the colors are stored in memory such that
R is at lowest address, G after that, B after that, and A last.
firmware: zynqmp: Move permission to change config object message
Move the permission to change a config object message from
zynqmp_pmufw_load_config_object function to zynqmp_pmufw_node function
to simplify the code and check the permission only if required.
firmware: zynqmp: Remove extraordinary return value
Return a common -EACCES error value instead of a positive private error
value XST_PM_NO_ACCESS (2002) in zynqmp_pmufw_load_config_object
function if the config object is not loadable to simplify the error
checking.
Michal Simek [Thu, 1 Jun 2023 10:32:36 +0000 (12:32 +0200)]
arm64: zynqmp: Check 0 node ID
ID is decimal not hexadecimal that's why passing hex number all the time
end's up as 0 that's why check it. Node ID 0 is not valid anyway.
Also properly say it in help.
Add missing prototypes to fix the below sparse warnings
1. warning: no previous prototype for 'soc_name_decode'
[-Wmissing-prototypes]
2. warning: no previous prototype for 'soc_detection'
[-Wmissing-prototypes]
3. warning: no previous prototype for 'board_name_decode'
[-Wmissing-prototypes]
4. warning: no previous prototype for 'board_detection'
[-Wmissing-prototypes]
Michal Simek [Wed, 17 May 2023 08:21:32 +0000 (10:21 +0200)]
arm64: versal-net: Add support for SPP production version
Production version restarting platform version field from 0 that's why add
new calculation to be able to use different DT for these platforms.
Requested DT names for production silicons for IPP/SPP and EMU platform are
versal-net-ipp-rev2.0.dts and versal-net-emu-rev2.0.dts.
If platform version increase numbers revision can be even higher.
As of today platform version is 2 that's why expected is rev2.2.
clk: zynqmp: Add fallthrough statement in the switch case
Add fallthrough statement in switch case to fix the sparse warning.
In function 'zynqmp_clk_get_rate': warning: this statement may
fall through [-Wimplicit-fallthrough=]
Hai Pham [Tue, 4 May 2021 10:43:23 +0000 (17:43 +0700)]
ARM: rmobile: Identify R-Car D3 R8A77995 r1.1 SoC
Add support to identify R8A77995 r1.1 SoC.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
[Marek: Slight update to commit message, spell out the SoC model]
r8a7796 cpu revision v1.2 has the same information as revision v1.1.
This patch fixes revision display at startup to "rev 1.1/1.2".
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
[Marek: Slight update to commit message, spell out the SoC model]
Sam Edwards [Thu, 8 Jun 2023 18:45:42 +0000 (12:45 -0600)]
usb: musb-new: sunxi: remove unused define
This is a remnant from when the USB controller driver managed
the reset signal itself. A patch from the very end of 2018 changed
this driver to delegate reset (and clock) management to the proper
control unit driver, but left this unused define behind.
Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de>
A small late pull request for Allwinner. The main feature is just a DT
update, matching the v6.4 Linux kernel DT files. This also enables a
board (LCTech Pi F1C200s) which got its .dts file merged into Linux.
Plus a tiny typo fix from Sam.
Gitlab CI passed, briefly tested on an H616 board and the new LCTech Pi.
Andre Przywara [Tue, 11 Apr 2023 22:56:14 +0000 (23:56 +0100)]
sunxi: defconfig: Add Lctech Pi F1C200s board
The Lctech Pi F1C200s (also previously known under the Cherry Pi brand)
is a small development board with the Allwinner F1C200s SoC. This is the
same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM.
Add a defconfig for this board, enabling the most basic features. This
uses the new 64MB memory map, which avoids the very tight memory map we
use for the 32MB F1C100s board(s).
The devicetree file is already in the tree, courtesy of the previous
Linux repo sync.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 2 Apr 2023 00:17:07 +0000 (01:17 +0100)]
sunxi: dts: arm/arm64: update devicetree files from Linux-v6.4-rc2
Sync the devicetree files from the official Linux kernel tree, v6.4-rc2.
This is covering both 64-bit and 32-bit Allwinner SoCs with Arm Ltd.
cores, we skip the new RISC-V bits for now, as sunxi RISC-V support
is still work in progress.
Among smaller cosmetic changes, this adds a SATA regulator node which we
need in U-Boot to get rid of hard-coded GPIOs.
Also this updates the Allwinner F1C100s DTs, enabling USB support, and
also adds the DTs for two new boards.
As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
phy: rockchip-inno-usb2: Implement clock operations for usb2phy clock
This clock doesn't seem needed but appears in a phandle list used by
ehci-generic.c to bulk enable it. The phandle list comes from linux,
where it is needed for suspend/resume to work [1].
My tests give the same results with or without this patch, but Marek
Vasut found it weird to declare an empty clk_ops [2].
So I adapted the code from linux 6.1-rc8 so that it hopefully works
if it ever has some user. For now, without real use, it seems to
at least not give any errors when called.
Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@vrull.eu> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Christoph Fritz <chf.fritz@googlemail.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # rk3399, rk3328, rv1126
Since clk_get_bulk() only looks for devices with UCLASS_CLK,
it fails with -ENODEV and then ehci_usb_probe() aborts.
The consequence is peripherals connected to a USB 2 port (e.g. in a
Rock Pi 4 the white port, nearer the edge) not being detected.
They're detected if CONFIG_USB_OHCI_GENERIC is selected in Kconfig,
because ohci_usb_probe() does not abort when one clk_get_by_index()
fails, but then they work in USB 1 mode.
rk3399.dtsi comes from linux and the u2phy0 was added[1] to the clock
list in:
arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399
We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.
[...]
Suspend concerns don't apply to U-Boot, and the problem with U-Boot
failing to probe EHCI doesn't apply to linux, because in linux
rockchip_usb2phy_clk480m_register makes u2phy0 a proper clock provider
when called by rockchip_usb2phy_probe().
So I can think of a few alternative solutions:
1- Change ehci_usb_probe() to make it more similar to
ohci_usb_probe(), and survive failure to get one clock. Looks a
little harder, and I don't know whether it could break something if
it ignored a clock that was important for something else than
suspend.
2- Change rk3399.dtsi effectively reverting the linux commit b5d1c57299734f5b54035ef2e61706b83041f20c. This dealigns the .dtsi
from linux and seems fragile at the next synchronisation.
3- Change the clock list in rk3399-u-boot.dtsi or somewhere else.
This survives .dts* sync but may survive "too much" and miss some
change from linux that we might want.
4- Enable CONFIG_USB_OHCI_GENERIC and use the ports in USB 1 mode.
This would need to be made for all boards using rk3399. In a
simple test reading one file from USB storage it gave 769.5 KiB/s
instead of 20.5 MiB/s with solution 2.
5- Trying to replicate linux and have usb2phy somehow provide a clk,
or have a separate clock device for usb2phy in addition to the phy
device.
This patch tries to implement option 5 as Marek Vasut requested in
December 5th. Options 1 and 3 didn't get through [2][3].
It just registers usb2phy as a clock driver (device_bind_driver()
didn't work but device_bind_driver_to_node() did), without any
specific operations, so that ehci-generic.c finds it and is happy. It
worked in my tests on a Rock Pi 4 B+ (rk3399).
Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@vrull.eu> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Christoph Fritz <chf.fritz@googlemail.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # rk3399, rk3328, rv1126
According to the dm_serial_ops documentation, pending() should:
> @return number of waiting characters, 0 for none, -ve on error
And:
> It is acceptable to return 1 if an indeterminant number
> of characters is waiting.
With the current implementation, we have:
* FIFO is full -> pending() returns 0
* FIFO is partially used -> pending() returns 1
* FIFO is empty -> pending() returns 1
This is not the same as what the documentation requires.
Moreover, since [1], arm reset now flushes all console devices
(including serial) before the cpu gets reset.
Because of the flawed logic:
=> reset # user calls reset
flush() is called
_serial_flush() is called
ops->pending(dev, false) # never returns false
# board hangs indefinitely without resetting.
Fix it by using AML_UART_TX_EMPTY instead of AML_UART_TX_FULL.
[1] commit c5f4cdb8eb60 ("console: Use flush() before panic and reset"),
Ben Dooks [Tue, 6 Jun 2023 08:23:28 +0000 (09:23 +0100)]
ubifs: allow loading to above 4GiB
The ubifsload command is truncating any address above 4GiB as it casts
this address to an u32, instead of using an unsigned long which most of
the other load commands do. Change this to an unsigned long to allow
loading into high memory for boards which use these areas.
Andrea Merello [Fri, 26 May 2023 14:56:16 +0000 (16:56 +0200)]
I2C: cdns: Fix broken retry mechanism on arbitration lost.
In the current implementation, in case of I2C arbitration lost, a retry is
attempted; the message counter and pointer are reset to the original values
and the I2C xfer process is restart from the beginning.
However the message counter and message pointer are respectively
decremented and incremented by one before attempting any transfer, causing
the 1st transfer not to be actually retried (in case of a single transfer,
nothing is actually retried at all).
This patch fixes this: in case of retry, the 1st transfer is also retried.
Tested on a ZynqMP Kria board, with upstream older u-boot, but the involved
file and underlying logic seem basically the same.
Signed-off-by: Andrea Merello <andrea.merello@iit.it>
Ondrej Jirman [Thu, 25 May 2023 12:18:17 +0000 (14:18 +0200)]
i2c: rockchip: De-initialize the bus after start bit failure
Failure can happen when i2c is used without initializing pinctrl properly,
which U-Boot happily allows in SPL. Without this fix, further I2C access would
fail, even after proper pinctrl initialization.
Signed-off-by: Ondrej Jirman <megi@xff.cz> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Mark Kettenis [Tue, 2 May 2023 19:30:41 +0000 (21:30 +0200)]
pci: apple: Add support for M2 Pro/Max
The PCIe controller on the M2 Pro/Max is different from the one
found on earlier Apple SoCs. Some registers moved and te meaning
of the bits in some other registers changed. But they are still
similar enough to handle both controllers in the same driver.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Mark Kettenis [Tue, 2 May 2023 19:30:40 +0000 (21:30 +0200)]
arm: apple: Add initial Apple M2 Pro/Max support
Apple's M2 Pro/Max SoC are somewhat similar to the M1 Pro/Max but
need a tweaked memory map. USB, NVMe, UART and WDT are working
with the existing drivers.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Manorit Chawdhry [Thu, 18 May 2023 07:14:17 +0000 (12:44 +0530)]
arm: mach-k3: security: separate out validating binary logic
K3 GP devices allows booting the secure binaries on them by bypassing
the x509 header on them.
ATF and OPTEE firewalling required the rproc_load to be called before
authentication. This change caused the failure for GP devices that
strips off the headers. The boot vector had been set before the headers
were stripped off causing the runtime stripping to fail and stripping
becoming in-effective.
Separate out the secure binary check on GP/HS devices so that the
boot_vector could be stripped before calling rproc_load. This allows
keeping the authentication later when the cluster is on along with
allowing the stripping of the binaries in case of gp devices.
Dave Gerlach [Tue, 16 May 2023 04:54:37 +0000 (10:24 +0530)]
arm: mach-k3: Increase SYSFW max image size
When booting with HS silicon, the system firmware image is 278270, which
is slightly larger than currently allocated amount.
This can cause unexpected behavior if this overlap interferes with other
things in memory, so increase this with a slightly margin added as well
to avoid any boot issues that can appear after system firmware gets
loaded.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com>
Manorit Chawdhry [Tue, 16 May 2023 04:54:36 +0000 (10:24 +0530)]
Kconfig: j721e: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region
In non-combined boot flow for K3, all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.
The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.
The commit changes R5 MCU scratchpad for j721e to an SRAM region.
Manorit Chawdhry [Tue, 16 May 2023 04:54:35 +0000 (10:24 +0530)]
configs: j721e: Merge the HS and non-HS defconfigs
K3 devices have runtime type board detection. Make the default defconfig
include the secure configuration. Then remove the HS specific config.
Non-HS devices will continue to boot due to runtime device type detection.
If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS
devices these can be ignored.
Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Acked-by: Andrew Davis <afd@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Andrew Davis [Tue, 16 May 2023 04:54:34 +0000 (10:24 +0530)]
arm: k3: config.mk: Add missing dependencies on tispl.bin HS
When building for secure devices using non-buildman based image generation
the signed tispl.bin file is called tispl.bin_HS. Also build the unsigned
tispl.bin file as expected.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Peng Fan [Fri, 28 Apr 2023 04:08:46 +0000 (12:08 +0800)]
imx9: imx93_evk: update ddr timing file
Update DDR timing file generated by DDR Config Tool
1. Dynamic refresh rate is set by default
2. The 3rd freq will be 625MTS based on power and performance better than 100MTS.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 28 Apr 2023 04:08:45 +0000 (12:08 +0800)]
imx9: Calculate DDR size from DDRC setting
To avoid using static setting for ECC enabled DDR size, switch
to calculate DDR size from DDRC setting
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Jacky Bai [Fri, 28 Apr 2023 04:08:43 +0000 (12:08 +0800)]
ddr: imx93: update the ddr init to support mult setpoints
Update the DDR init flow for multi-setpoint support on i.MX93. A new
fsp_cfg struct need to be added in the timing file to store the diff
part of the DDRC and DRAM MR register for each setpoint.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Jacky Bai [Fri, 28 Apr 2023 04:08:41 +0000 (12:08 +0800)]
ddr: imx9: Change the saved ddr data base to 0x2051c000
change the ddr saved info to the last 16KB of the OCRAM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 28 Apr 2023 04:08:39 +0000 (12:08 +0800)]
ddr: imx9: Add workaround for DDRPHY rank-to-rank errata
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap
specification does not include the Critical Delay Difference (CDD) to
properly define the required rank-to-rank read command spacing after
executing PHY training firmware.
Following the errata workaround, at the end of data training, we get
all CDD values through the MessageBlock, then re-configure the DDRC
timing of WWT/WRT/RRT/RWT with comparing MAX CDD values.
Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 28 Apr 2023 04:08:36 +0000 (12:08 +0800)]
imx9: allow to bootaux Mcore with input address
Currently bootaux only supports to boot M33 core from TCM. Since ATF
has changed to use x2 parameter for M33 image address, update the
bootaux command to use input address, so we can support boot from
any possilbe address like TCM, DDR, Flexspi NOR.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 28 Apr 2023 04:08:35 +0000 (12:08 +0800)]
imx9: imx93_evk: add low drive mode support on 11x11 EVK
Add a static u-boot config for i.MX93 low drive mode support. When
low drive mode is enabled, VDD_SOC is set to 0.75V. Bus clocks,
A55 core clock (900Mhz), DDR clock (1866MTS), and some peripherals
clocks (USDHC/FLEXSPI/PDM/DISP_PIX/CAM_PIX) must decrease to meet
max frequencies in low drive mode.
Also set standby voltage for buck1
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 28 Apr 2023 04:08:32 +0000 (12:08 +0800)]
imx9: add i.MX93 variants support
According to datasheet, iMX93 has fused parts with CORE1 or NPU or
both disabled. So update code to support it, the kernel device tree
runtime update will be added in future patches.
Peng Fan [Fri, 28 Apr 2023 04:08:31 +0000 (12:08 +0800)]
imx9: clock: config arm alt root to 500mhz
Config the A55 alt root clock to 500MHz(LD mode frequency)
by default. Normally, this clock root is only used as an
intermediate clock soure for A55 core/dsu when change the
ARM PLL frequency.
Peng Fan [Fri, 28 Apr 2023 04:08:20 +0000 (12:08 +0800)]
imx9: cut off OPTEE memory region from U-Boot
OPTEE memory region is set secure access only in ATF with configuration
to TRDC, and need to remove it from U-Boot, otherwise U-Boot and Kernel
may crash when accessing the memory
Peng Fan [Fri, 28 Apr 2023 04:08:09 +0000 (12:08 +0800)]
imx: move imx8 sci header file to include/firmware/imx
Move imx8 sci header file to include/firmware/imx, then we could
use build macro to reuse some i.MX8 drivers for i.MX9, such as
drivers/cpu/imx8_cpu.c.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
projects / u-boot.git / log