mmc: zynq_sdhci: Add clock phase delays for Versal
Define default values for input and output clock phase delays for
Versal. Also define functions for setting tapdelays based on these
clock phase delays.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Define timing macro's for all the available speeds of mmc. This is
done similar to linux. Replace speed macro's used with these new timing
macro's wherever applicable.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
mmc_of_parse() is reading no-1-8-v from device tree and if set,
it is clearing the UHS speed capabilities of cfg->host_caps.
cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 |
MMC_MODE_HS400 | MMC_MODE_HS400_ES);
This is still missing to clear UHS speeds like SDHCI_SUPPORT_SDR104,
SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50.
Even if we clear the flags SDHCI_SUPPORT_XXX in mmc_of_parse(),
these speed flags are getting set again in cfg->host_caps in
sdhci_setup_cfg().
The reason for this is, SDHCI_SUPPORT_XXX flags are cleared
only if controller is not capable of supporting MMC_VDD_165_195 volts.
if (caps & SDHCI_CAN_VDD_180)
cfg->voltages |= MMC_VDD_165_195;
It means "no-1-8-v", which is read from DT is not coming in to effect.
So it is better we keep the host quirks(SDHCI_QUIRK_NO_1_8_V) to
clear UHS speeds based on no-1-8-v from device tree.
Hence revert the functionality related to no-1-8-v only, rest is fine
in the patch.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add function description for zynq_qspi_init_hw and zynq_qspi_chipselect.
Fix zqspi to priv in function descriptions.
Change the description of priv as pointer to zynq_qspi_priv structure.
Fix other function descriptions to kernel-doc style.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Call generic board_late_init_xilinx() to be aligned with the rest of xilinx
platforms. Also getting rid of initrd_high/fdt_high and use
bootm_low/boot_size instead.
Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 22 Oct 2020 08:59:08 +0000 (10:59 +0200)]
xilinx: zynq: Change types from u32 to uint32_t
Change parameter type to avoid compilation error:
In file included from ./tools/../lib/rsa/rsa-verify.c:23:0,
from tools/lib/rsa/rsa-verify.c:1:
include/u-boot/rsa-mod-exp.h:69:18: error: unknown type name ‘u32’; did you mean ‘__u32’?
int zynq_pow_mod(u32 *keyptr, u32 *inout);
^~~
__u32
include/u-boot/rsa-mod-exp.h:69:31: error: unknown type name ‘u32’; did you mean ‘__u32’?
int zynq_pow_mod(u32 *keyptr, u32 *inout);
^~~
__u32
Fixes: 37e3a36a5475 ("xilinx: zynq: Add support to secure images") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
xilinx: Add DDR base address to bootscript address
Add ram base address to scriptaddr env variable to make boot
script address to be a valid address when ddr base address changes.
This works properly if the first memory region is the region where uboot
runs. Also the solution was taken in respect of a lot of jtag script
putting u-boot script to certain address. For standard cases
bd->bi_dram[0].start is 0 all the time. Only for systems with DDR placed
out of this location it does calculation.
This is not the best solution and should be done differently in future but
enough for now till we don't have full solution ready yet.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
For zynqmp qspi, frequencies up to 40MHz will work irrespective
of feedback clock enabled or disabled. If we want higher than
40Mhz the feedback clock should be enabled.
With spi-max-frequency 108MHz it is not working when the feedback
clock is disabled. Change it to 40MHz so that it works irrespective
of feedback clock enabled or disabled.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 21 Oct 2020 10:17:44 +0000 (12:17 +0200)]
xilinx: zynqmp: Do not check 0 as invalid return from snprintf
U-Boot SPL on ZynqMP is using CONFIG_SPL_USE_TINY_PRINTF which doesn't
return any return value and all the time returns 0. That's why
even correct snprintf was returning in SPL chip ID as "unknown".
Change checking condition and allow snprintf to return 0 which is according
manual patch successful return.
"If an output error is encountered, a negative value is returned."
Fixes: 43a138956f7e ("arm64: zynqmp: Get rid of simple_itoa and replace it by snprintf") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 15 Apr 2019 11:54:09 +0000 (13:54 +0200)]
xilinx: cmd: Add basic fru format generator
Idea is to have something what can be used for board bringup from
generic board perspective.
There is a violation compare to spec that FRU ID is ASCII8 instead of
binary format but this is really for having something to pass boot and
boot to OS which has better generating options.
Also time should be filled properly.
For example:
fru board_gen 1000 XILINX versal-x-prc-01-revA serialX partX
There is also support for revision field which is Xilinx specific field.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support for fru commands "fru capture" and "fru display".
The fru capture parses the FRU table present at an address and stores in a
structure for later use. The fru display prints the content of captured
structured in a readable format.
As of now, it supports only common header and board area of FRU. Also, it
supports only English language code and ASCII8/BINARY formats.
fru_data variable is placed to data section because fru parser can be
called very early before bss is initialized. And also information needs to
be shared that's why it is exported via header.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 20 Oct 2020 10:05:14 +0000 (12:05 +0200)]
xilinx: common: Add Makefile to common folder
There is no need to reference files in common folder back. Simply adding
Makefile to this folder does the job because this "common" location is
already wired in main Makefile.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 14 Oct 2020 15:08:14 +0000 (17:08 +0200)]
xilinx: common: Move ZYNQ_GEM_I2C_MAC_OFFSET to board Kconfig
There is no reason to have ZYNQ specific Kconfig macro in generic location
to be visible for all other SoCs. That's why move it to Xilinx common
location to be visible only for us.
Also introduce new bool entry ZYNQ_MAC_IN_EEPROM to have also an option to
disable it or enable. This has connection to code which is reading the
whole content of i2c and also work with the rest of date not just with MAC
address.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 3 Sep 2020 10:44:51 +0000 (12:44 +0200)]
spl: fdt: Record load/entry fit-images entries in 64bit format
The commit 9f45aeb93727 ("spl: fit: implement fdt_record_loadable") which
introduced fdt_record_loadable() state there spl_fit.c is not 64bit safe.
Based on my tests on Xilinx ZynqMP zcu102 platform there shouldn't be a
problem to record these addresses in 64bit format.
The patch adds support for systems which need to load images above 4GB.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Thu, 3 Sep 2020 09:24:28 +0000 (11:24 +0200)]
spl: Use standard FIT entries
SPL is creating fit-images DT node when loadables are recorded in selected
configuration. Entries which are created are using entry-point and
load-addr property names. But there shouldn't be a need to use non standard
properties because entry/load are standard FIT properties. But using
standard FIT properties enables option to use generic FIT functions to
descrease SPL size. Here is result for ZynqMP virt configuration:
xilinx_zynqmp_virt: spl/u-boot-spl:all -82 spl/u-boot-spl:rodata -22 spl/u-boot-spl:text -60
The patch causes change in run time fit image record.
Before:
fit-images {
uboot {
os = "u-boot";
type = "firmware";
size = <0xfd520>;
entry-point = <0x8000000>;
load-addr = <0x8000000>;
};
};
T Karthik Reddy [Tue, 4 Feb 2020 12:47:45 +0000 (05:47 -0700)]
spi: zynq_qspi: Use clk subsystem to get reference qspi clk
Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 4 Feb 2020 12:47:44 +0000 (05:47 -0700)]
spi: zynq_spi: Use clk subsystem to get reference spi clk
Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 3 Aug 2020 10:57:05 +0000 (12:57 +0200)]
xilinx: board: Add support for additional card detection
The most of Xilinx evaluation boards have FMC connectors which contain
small eeprom for card identification. That's why read content of eeprom and
record it.
Also generate cardX_ variables for easier script handling.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 3 Aug 2020 11:01:45 +0000 (13:01 +0200)]
xilinx: board: Read the whole eeprom not just offset
Starts to use new way how eeproms should be referenced.
Reference is done via nvmem alias nodes. When this new way is specified
code itself read the eeprom and decode xilinx legacy format and fill struct
xilinx_board_description. Then based on information present there board_*
variables are setup.
If variables are saved and content can't be changed information is just
shown on console.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 20 Oct 2020 06:29:25 +0000 (08:29 +0200)]
arm64: zynqmp: Add support for saving sha3 key to different address
By default 48B sha3 hash value is written to srcaddr which is not the best
solution in case of that you want to use data for other operations. That's
why add key_addr optional parameters which enables to write 48B sha3 hash
value to specified address.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
arm64: zynqmp: Add support for encryption and decryption on data blob
This patch adds support for encryption and decryption on a given data
blob using different key sources such as userkey(KUP), device key and
PUF key. Inorder to support this a new zynqmp command(zynqmp aes) has
been introduced.
Command:
zynqmp aes srcaddr ivaddr len aesop keysrc dstaddr [keyaddr]\n"
Encrypts or decrypts blob of data at src address and puts it\n"
back to dstaddr using key and iv at keyaddr and ivaddr\n"
respectively. keysrc values specifies from which source key\n"
has to be used, it can be User/Device/PUF key. A value of 0\n"
for KUP(user key),1 for DeviceKey and 2 for PUF key. The\n"
aesop value would specify the operationwhich can be 0 for\n"
decrypt and 1 for encrypt(1) operation\n";
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 7 Oct 2020 13:53:39 +0000 (15:53 +0200)]
arm64: zynqmp: Get rid of iommus/power-domains properties for SPL DT
SPL DT contains only nodes which are contain u-boot,dm-pre-reloc property.
iommu node is not this case that's why when DT is read DTC reports some
warnings.
$ dtc -I dtb -O dts dts/dt-spl.dtb >/dev/null
<stdout>: Warning (iommus_property): /amba/spi@ff0f0000:iommus: Could not get phandle node for (cell 0)
<stdout>: Warning (iommus_property): /amba/mmc@ff160000:iommus: Could not get phandle node for (cell 0)
<stdout>: Warning (iommus_property): /amba/mmc@ff170000:iommus: Could not get phandle node for (cell 0)
SPL also has an option to remove some DT properties which are useless for
SPL to make DT even smaller.
Default DT properties are pinctrl-0 pinctrl-names interrupt-parent
interrupts which are already removed.
The patch extends this list with iommus to get rid of above warnings.
Also power-domains unused properties can be removed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 5 Oct 2020 13:43:44 +0000 (15:43 +0200)]
arm64: zynqmp: Enable FPGA loading from SPL
fpga bitstream needs to be listed in config node in FIT image. Only tested
option is bitstream in BIN format.
Enabling this feature increase code size by almost 4k.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 7 Oct 2020 13:13:17 +0000 (15:13 +0200)]
arm64: zynqmp: Get rid of simple_itoa and replace it by snprintf
simple_itoa() is implemented only for !CONFIG_USE_TINY_PRINTF. Tiny printf
is normally used by SPL that's code which uses simple_itoa() has missing
reference. That's why refactor code by using on snprintf() instead of
strncpy()/strncat() combination. This change also descrease code size by
saving 24B based on buildman.
aarch64: (for 1/1 boards) all -22.0 rodata +2.0 text -24.0
xilinx_zynqmp_virt: all -22 rodata +2 text -24
u-boot: add: 0/0, grow: 0/-1 bytes: 0/-24 (-24)
function old new delta
board_init 520 496 -24
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 5 Oct 2020 13:23:28 +0000 (15:23 +0200)]
firmware: zynqmp: Swap addr_hi/low when PM_FPGA_LOAD is called
Don't know reason but in regular flow addr_hi/low are swapped in ATF. It
means when fpga load is done from EL3 there is a need to swap it for PMUFW
to load bitstream.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
config: versal: Update mini u-boot timer clock to 100Mhz
Mini u-boot timer clock is not updated when u-boot is migrated from
emulator to silicon. Due to this slower clock of 2.72Mhz, delay() functions
are not working accurately. Update CONFIG_COUNTER_FREQUENCY to 100Mhz.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add distro boot support for microblaze and enable jtag, qspi,
dhcp, pxe boot targets for distro boot.
Enable DISTRO_DEFAULTS config in microblaze defconfig and also
enable support for spi xilinx driver & spi vendors to access
spi flash by distro boot.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Adding Z-turn board V5 to resolve the change between:
"Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
"Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031
At this time the S25FL128SAGNFI003 doesn't work because of bug:
*** Warning - spi_flash_probe_bus_cs() failed, using default environment
zynq-zturn was checked on V5 board, same error.
Maybe Z-turn board have the same problem (board with W25Q128BVFIG).
Signed-off-by: Alexandre GRIVEAUX <agriveaux@deutnet.info> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
microblaze: start.S: Use board_init_f_alloc/init in early init
Implement early init by calling generic board_init_f_alloc_reserve and
board_init_f_init_reserve functions:
* drop SYS_MALLOC_F_LEN related code, as allocation and gd->malloc_base
assignment are taken care of by the generic functions
* drop _gd logic
Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
microblaze: start.S: Factor out exception setup code to __setup_exceptions
Currently, the exceptions setup code is duplicated in pre-relocation and
post-relocation init. Factor out this code to __setup_exceptions asm
routine to get rid of the duplication.
__setup_exceptions is called with a relocation offset parameter (r5)
which is set to zero for pre-reloc init and gd->reloc_off for post-reloc
exception setup.
Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tom Rini [Sat, 24 Oct 2020 14:49:28 +0000 (10:49 -0400)]
Merge branch '2020-10-23-misc-changes'
Highlights:
- Fix a problem with the bootm overlap tests
- Remove duplicated code in fatwrite
- Cleanup our current "misc" command code and add a new one for misc
class devices.
- Various GPIO fixes
Jaehoon Chung [Wed, 21 Oct 2020 05:17:03 +0000 (14:17 +0900)]
bootm: fix wrong conditions about images overlap
It doesn't need to consider start byte address.
If ramdisk size is 0x800000 and start address is 0x2700000, then it's
used until 0x02efffff, not 0x02f00000. But it's detected to overlapt RD
image, when kernel start address is 0x02f00000.
Because it's doing wrong calculation about rd_len.
This patch fixed wrong calculation address position when check
condition.
In addition, it needs to check one more condition about overlapping
entire area.
Fixes: commit fbde7589ce30 ("common: bootm: add checks to verify if ramdisk / fdtimage overlaps OS image") Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Bin Meng [Wed, 14 Oct 2020 06:34:52 +0000 (14:34 +0800)]
cmd: Add a 'misc' command to access miscellaneous devices
Enable the command "misc" for accessing miscellaneous devices with
a MISC uclass driver. The command provides listing all MISC devices
as well as read and write functionalities via their drivers.
Pali Rohár [Wed, 7 Oct 2020 13:39:40 +0000 (15:39 +0200)]
Makefile: Fix u-boot-nodtb.bin target
This change fixes two issues when building u-boot-nodtb.bin target:
* Remove intermediate binary u-boot-nodtb.bin from disk when static_rela
call (which modifies u-boot-nodtb.bin binary) failed. It is required
because previous objcopy call creates binary and static_rela finish it.
* Do not call static_rela cmd when u-boot-nodtb.bin binary was not
created/updated by previous objcopy call.
Second fix would ensure that u-boot-nodtb.bin binary is not updated when
all prerequisites were up-to-date. And therefore final binary u-boot.bin
is not updated in case all prerequisites were not modified and were
up-to-date.
Now running 'make SOURCE_DATE_EPOCH=0 u-boot.bin' second time now does not
touch u-boot.bin binary in case nothing was modified, so GNU make can
correctly detect that everything is up-to-date.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 22 Oct 2020 18:36:47 +0000 (14:36 -0400)]
Merge branch '2020-10-22-misc-changes'
- Assorted updates for Xen, IPQ40xx, ASpeed, Keymile
- Assorted typo / documentation fixes
- Fix default preboot cmd to act like before with USB_STORAGE set
- A number of other bugfixes throughout the code
AKASHI Takahiro [Thu, 15 Oct 2020 04:25:14 +0000 (13:25 +0900)]
arch: arm/xen: add putc() for debugging
This new function, xen_debug_putc(), is intended to be used to
enable CONFIG_DEBUG_UART on xen guest.
Please note that the underlying functionality in Xen is available
only when Xen is configured with !NDEBUG but is much simpler than
a generic HYPERVISOR_console_io().
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Chia-Wei, Wang [Thu, 15 Oct 2020 02:25:13 +0000 (10:25 +0800)]
reset: ast2500: Use SCU for reset control
The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.
This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.
The Kconfig description is also updated accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
Dario Binacchi [Wed, 14 Oct 2020 21:42:17 +0000 (23:42 +0200)]
clk: ccf: replace the get_rate helper
The 12d152620d commit fixed the get_rate helper because the set_parent
one did not re-parent the clock device to the new parent. The 4d139f3838
commit allows you to remove this workaround by calling the
clk_get_parent_rate routine.
projects / u-boot.git / log