Simon Glass [Mon, 21 Jan 2019 21:53:27 +0000 (14:53 -0700)]
rockchip: Clarify docs on SPI writing
We use every second block when creating a SPI image, so update the text to
say this explicitly.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Simon Glass [Mon, 21 Jan 2019 21:53:26 +0000 (14:53 -0700)]
rockchip: evb_rk3399: Tidy up the README
Add mention of a prerequisite needed to build the image. Also adjust the
English wording in a few places.
Ideally this should move to using binman to produce images, and avoid the
manual steps.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Simon Glass [Mon, 21 Jan 2019 21:53:25 +0000 (14:53 -0700)]
rockchip: Adjust rk3399 device tree to be closer to linux
This file has changed upstream, with some additions and changes. Move the
U-Boot version towards this.
Some USB changes seem to be incompatible with how the bindings work on
rockchip in U-Boot. Testing is needed to make sure that USB still works
correct, and adjust the code (not device tree) if not.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Simon Glass [Mon, 21 Jan 2019 21:53:23 +0000 (14:53 -0700)]
rockchip: Drop note about supporting other SoCs
Quite a wide range of Rockchip SoCs are supported in mainline U-Boot now,
so drop the comment about needing to add more.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Simon Glass [Mon, 21 Jan 2019 21:53:22 +0000 (14:53 -0700)]
rockchip: Add mention of other boards
At present some Rockchip SoCs and boards are not mentioned in the README.
So that people can see which SoCs are supported, expand the list to
include everything.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Simon Glass [Mon, 21 Jan 2019 21:53:21 +0000 (14:53 -0700)]
gpio: Add a simple GPIO API for SPL
In space-constrained environments or before driver model is available, it
is sometimes necessary to set GPIO values. Add an SPL API for this, to
allow early board code to change GPIOs. The caller must provide the
register address, so that the drivers can be fairly generic.
This API can be implemented by GPIO drivers, behind a suitable guard,
like #ifdef CONFIG_SPL_BUILD.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Simon Glass [Mon, 21 Jan 2019 21:53:20 +0000 (14:53 -0700)]
gpio: Use more command-specific enums values
At present this file uses GPIO_OUTPUT and GPIO_INPUT as its sub-command
values. These are pretty generic names. Add a 'C' suffix to avoid possible
conflicts.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Simon Glass [Mon, 21 Jan 2019 21:53:19 +0000 (14:53 -0700)]
clk: Improve debug message in clk_set_default_rates()
It is helpful to print the clock number as well as the index, so that this
can be looked up in the binding file. Update the debug() statement to do
this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Simon Glass [Mon, 21 Jan 2019 21:53:18 +0000 (14:53 -0700)]
lib: Allow using display_buffer() in SPL
At present this function uses printf() format strings that are not
supported in SPL, so the output just consists of %llx strings on 64-bit.
machines. Fix this by adding a special case.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 2 Jan 2019 13:02:35 +0000 (21:02 +0800)]
ARM: dts: rk322x: Correct the uart2 default pin configuration
To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.
Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 2 Jan 2019 13:02:23 +0000 (21:02 +0800)]
pinctrl: rockchip: Clean the unused rockchip pinctrl drivers
If we used the pinctrl-rockchip driver, these code is not needed,
so remove them.
Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 2 Jan 2019 13:01:55 +0000 (21:01 +0800)]
rockchip: defconfig: Clean the unused pinctrl config
If we used the pinctrl-rockchip driver, these config is not needed,
so remove them.
Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 2 Jan 2019 12:51:00 +0000 (20:51 +0800)]
ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.
Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 2 Jan 2019 12:50:59 +0000 (20:50 +0800)]
ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188
It seems that pinctrl is not requested for rk3188 SPL, remove it so
that can save more space for SPL image size.
Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 2 Jan 2019 12:50:58 +0000 (20:50 +0800)]
ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.
Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Wed, 2 Jan 2019 12:50:57 +0000 (20:50 +0800)]
rockchip: rk3399-evb: defconfig: Enable FDT for new pinctrl driver
The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA
to make FDT be built in.
Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
rockchip: add support for veyron-speedy (ASUS Chromebook C201)
This adds support for the ASUS C201, a RK3288-based clamshell
device. The device tree comes from linus's linux tree at 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
are for 4GB Samsung LPDDR3, decoded from coreboot's
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Simon Glass [Sat, 29 Dec 2018 13:16:41 +0000 (06:16 -0700)]
rockchip: Drop call to rockchip_dnl_mode_check() for now
This function causes a 5-second delay and stops the display working on
minnie. This code should be in a driver and should only be enabled by
a device-tree property, so that it does not affect devices which do not
have this feature.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Simon Glass [Fri, 28 Dec 2018 03:15:21 +0000 (20:15 -0700)]
rockchip: Add an I2S driver
Add a driver for I2S which allows audio data to be sent from the SoC to
the audio codec. The sample rate and other settings are hard-coded for now
as there is no suitable device-tree binding available.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tom Rini [Thu, 31 Jan 2019 12:19:52 +0000 (07:19 -0500)]
Merge tag 'u-boot-amlogic-20190131' of git://git.denx.de/u-boot-amlogic
- Add features and fixups to support video on Amlogic GX SoCs
- Add video support for Amlogic GX SoC
- Add DT fixups
- Enable Video and USB Console for libretech-cc board
Maxime Jourdan [Thu, 20 Dec 2018 14:09:12 +0000 (15:09 +0100)]
arm: meson64: enable console mux and console env by default
With the recent addition of the meson VPU driver, enable the following
config entries by default for meson-64 targets: CONFIG_CONSOLE_MUX,
CONFIG_SYS_CONSOLE_IS_IN_ENV.
This allows outputting the console via video if CONFIG_VIDEO_MESON is
selected.
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Anatolij Gustschin <agust@denx.de>
Neil Armstrong [Tue, 6 Nov 2018 08:30:14 +0000 (09:30 +0100)]
arm64: dts: meson-gx: Add hdmi_5v regulator as hdmi tx supply
The hdmi_5v regulator must be enabled to provide power to the physical HDMI
PHY and enables the HDMI 5V presence loopback for the monitor.
Fixes: b409f625a6d5 ("ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boards") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
[backport of linux commit e1f2163deac059ad39f07aba9e314ebe605d5a7a]
dfu: mmc: call fs functions instead of run_command
This unbreaks dfu mmc_file_op which is currently broken since using the
load cmd on a buffer from heap is not allowed - added with
commit aa3c609e2be5 ("fs: prevent overwriting reserved memory")
Fixes: commit aa3c609e2be5 ("fs: prevent overwriting reserved memory") Reported-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Lukasz Majewski <lukma@denx.de>
Jagan Teki [Tue, 29 Jan 2019 15:54:15 +0000 (15:54 +0000)]
arm: sunxi: Enable DM_MMC
Enable DM_MMC for all Allwinner SoCs, this will eventually
enable BLK.
Also removed DM_MMC enablement in few parts of sunxi
configurations.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Jagan Teki [Fri, 25 Jan 2019 08:28:25 +0000 (13:58 +0530)]
sunxi: A64: pinebook-u-boot: Include sunxi-u-boot.dtsi
Like other Allwinner A64 boards, pinebook also need altering
auto-numbering of mmc2 to mmc1 which is available in common
sunxi dsti file, sunxi-u-boot.dtsi
Pinebook has a separate sun50i-a64-pinebook-u-boot.dtsi which
takes more precedence for u-boot.dtsi inclusion and it eventually
failed to include the sunxi-u-boot.dtsi.
So, this patch add support to include the sunxi-u-boot.dtsi in the
sun50i-a64-pinebook-u-boot.dtsi
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> # Pinebook
Jagan Teki [Mon, 21 Jan 2019 10:31:15 +0000 (16:01 +0530)]
arm: dts: sunxi: Alter mmc2 auto-numbering to mmc1
Environment and fastboot mmc devices are configured based on the number
of mmc slots defined on particular board configs, MMC_SUNXI_SLOT_EXTRA.
If MMC_SUNXI_SLOT_EXTRA is more than 1, the default env and fastboot
mmc devices is mmc1 by assuming mmc0 is SD and mmc1 is emmc device.
But with DM_MMC the mmc devices are numbered as per the dts node
enablement. If there is a chance of having enabling all mmc nodes
in dts say mmc0, mmc1, mmc2 then the default env and fastboot devices
will failed to assign proper emmc device since mmc2 is emmc in most
of the Allwinner platforms.
So, we need to alter the auto-numbering by aliasing mmc2 to mmc1 since
aliases take precedence over auto-numbering.
If the dts enables mmc0, mmc1, mmc2, then all the nodes will probe
sequentially and auto-numbered as it is. but when aliases mmc1 with mmc2
the resulting number should be that mmc0 is till mmc0, mmc2 become mmc1
and mmc2 become mmc1
Without aliases of mmc1 = &mmc2;
-------------------------------
MMC: mmc@1c0f000: 0, mmc@1c10000: 1, mmc@1c11000: 2
With aliases of mmc1 = &mmc2;
----------------------------
MMC: Device 'mmc@1c11000': seq 1 is in use by 'mmc@1c10000'
mmc@1c0f000: 0, mmc@1c10000: 2, mmc@1c11000: 1
Loading Environment from FAT... OK
Some platforms like A20 has mmc0...mmc3, but there is no usecases now
for enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Tue, 29 Jan 2019 15:54:08 +0000 (15:54 +0000)]
sunxi: clk: enable clk and reset for CCU devices
Some Allwinner clock devices have parent clocks and reset gates itself,
which need to be activated for them to work.
Add some code to just assert all resets and enable all clocks given.
This should enable the A80 MMC config clock, which requires both to be
activated. The full CCU devices typically don't require resets, and have
just fixed clocks as their parents. Since we treat both as optional and
enabling fixed clocks is a NOP, this works for all cases, without the need
to differentiate between those clock types.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
Andre Przywara [Tue, 29 Jan 2019 15:54:14 +0000 (15:54 +0000)]
sunxi: board: do MMC pinmux setup for DM_MMC builds
Enabling DM_MMC skips the call to mmc_pinmux_setup() in board.c, as this
is supposed to be handled by the MMC driver, using DT information.
However we don't have a pinctrl driver yet, but would still like to keep
the working pinmux setup for our MMC devices. So bring this particular
call back to the DM_MMC code flow.
When booting from either SD card or eMMC, the SPL does the setup for us,
but when booting from SPI or USB we must not skip this part.
Fixes, boot via FEL or SPI flash, where the SPL won't setup the pinmux
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
[jagan: add Fix details on commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Tue, 29 Jan 2019 15:54:13 +0000 (15:54 +0000)]
mmc: sunxi: Add DM clk and reset support
Now that we have the gate clocks and the reset gates in our new
Allwinner clock driver, let's make use of them in the MMC driver, when
DM_MMC is defined.
We treat the reset device as optional now, as the older SoCs don't
implement it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Jagan Teki [Tue, 29 Jan 2019 15:54:12 +0000 (15:54 +0000)]
mmc: sunxi: Add DM_MMC support for H6
Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset.
Connect that with the respective compatible string.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Jagan Teki [Tue, 29 Jan 2019 15:54:11 +0000 (15:54 +0000)]
mmc: sunxi: Add remaining compatible strings
Add MMC compatible strings for A83T, A64, H5.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 29 Jan 2019 15:54:10 +0000 (15:54 +0000)]
sunxi: clk: A80: add MMC clock support
The A80 handles resets and clock gates for the MMC devices differently,
outside of the CCU IP block. Consequently we have a separate clock
device with a separate binding for that.
Implement that with the respective clock gates and resets to allow the
A80 taking part in the DM_MMC game.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: fix a80 mmc clock config compatible] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Patrick Delaunay [Mon, 28 Jan 2019 10:13:27 +0000 (11:13 +0100)]
arm: stm32mp1: deploy spl in root folder
Update generation of spl binaries
- continue to generate all SPL files in spl sub-directory
- copy in root folder the needed file for user (YOCTO, buildroot):
u-boot-spl.stm32
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Jerome Brunet [Fri, 4 Jan 2019 14:44:34 +0000 (15:44 +0100)]
pinctrl: meson: add pinconf support
Adding pinconf support is necessary to enable boot from SPI
without breaking the eMMC. When booting from SPI, the ROM code
leave pull downs on the eMMC pad.
We need to set pinconf provided in DT to solve this
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added missing comma in pinctrl-meson-axg-pmx.c]
Priit Laes [Fri, 18 Jan 2019 13:56:51 +0000 (15:56 +0200)]
videomodes: Relax EDID validation checks for hsync/vsync pulse width
Current EDID detailed timing parser errors out when either
horizontal or vertical pulse sync width is 0, thus not
allowing a display with EDID listed below work properly.
EDID below works ok within Linux although it warns about
these two fields being 0. Therefore relax the checks a bit
so we can actually use this the screen out of the box.
Of-course, this display itself is somewhat quirky display with
following anti-features:
- HPD pin is not usable
- although resolution is 640x480, only top 240 pixels are visible
Adam Ford [Fri, 28 Dec 2018 16:24:15 +0000 (10:24 -0600)]
ARM: imx6q_logic: Enable Falcon Mode and fatwrite
This patch enables Falcon Mode by default and updates the README
file to show instructions on how to run from the micro SD card
or eMMC. This patch also enables fatwrite to help assist with
writing the 'args' to the microSD card.
Adam Ford [Fri, 28 Dec 2018 14:55:41 +0000 (08:55 -0600)]
ARM: DTS: imx6q-logicpd: Update DTS/DTSI files
The i.MX6 SOM and development kits have undergone significant
updates and changes over the past few months. This re-sync's
the U-Boot with Logic PD's BSP.
Adam Ford [Fri, 28 Dec 2018 14:47:40 +0000 (08:47 -0600)]
imx6q_logic: Enable MMC booting from SPL
The MMC booting wasn't previously fitting into the codespace.
This patch enables MMC booting from the baseboard by reducing
some DM overhead during SPL.
Bryan O'Donoghue [Fri, 18 Jan 2019 17:40:11 +0000 (17:40 +0000)]
arm: dts: imx7s-warp: Create alias for mmc0 to &usdhc3
This patch sets up an alias for mmc0 to usdhc3.
Before the DM conversion only usdhc3 was enabled and therefore it appeared
as MMC 0 to u-boot. After enabling MMC DM though usdhc3 defaults to MMC 2,
which left unattended would drive changes to existing warp7 bootscripts and
environment variables that rely on mmc 0.
Setup the alias of mmc0 and usdhc3 so that existing warp7 boot code will
work unmodified.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Peng Fan <peng.fan@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Fri, 18 Jan 2019 08:58:38 +0000 (08:58 +0000)]
imx8: cpu: restrict checking ROM passover info for revA
Passover info only for revA.
move get_cpu_rev out of CONFIG_CPU to avoid build failure when using
get_cpu_rev in SPL.
Add a CONFIG_SPL_BUILD for passover usage, no need to execute it again
in normal U-Boot stage. Also if still checking passover info in normal
U-Boot stage, need to make the passover code executed after
arch_cpu_init_dm.
So to make it easy and clean, only execute the code for SPL stage.
Ye Li [Mon, 7 Jan 2019 09:29:21 +0000 (09:29 +0000)]
imx: Check the PL310 version for applying errata
Apply errata based on PL310 version instead of compile
time. Also set Prefetch offset to 15, since it improves
memcpy performance by 35%. Don't enable Incr double
Linefill enable since it adversely affects memcpy
performance by about 32MB/s and reads by 90MB/s. Tested
with 4K to 16MB sized src and dst aligned buffer.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ye Li <ye.li@nxp.com>
Lukasz Majewski [Thu, 3 Jan 2019 22:50:51 +0000 (23:50 +0100)]
ARM: imx: fix: Provide correct enum values for ONENAND/NOR boot recognition
According to "Table 5-1. Boot Device Select" (page 335,
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 4, 09/2017)
the BOOT_CFG1[3] have following values (regarding EIM booting):
0 - NOR flash and 1 - ONENAND
This commit provides correct identification of the boot medium for IMX6Q
boards booting from NOR memory (MCCMON6 is one of them).
Adam Ford [Sun, 30 Dec 2018 16:11:16 +0000 (10:11 -0600)]
MTD: nand: mxs_nand_spl: Fix empty function pointer for BBT
The initialization function calls a nand_chip.scan_bbt(mtd) but
scan_bbt is never initialized resulting in an undefined function
pointer. This will direct the function pointer to nand_default_bbt
defined in the same file.
Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
Ye Li [Fri, 4 Jan 2019 09:26:00 +0000 (09:26 +0000)]
spi: mxc_spi: Fix build warning on ARM64 platforms
When building mxc_spi driver on ARM64 platforms, get below build warnings.
Fix it in this patch.
In file included from include/common.h:48:0,
from drivers/spi/mxc_spi.c:9:
drivers/spi/mxc_spi.c: In function ‘spi_xchg_single’:
drivers/spi/mxc_spi.c:232:21: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
_func_, bitlen, (u32)dout, (u32)din);
^
include/log.h:135:26: note: in definition of macro ‘debug_cond’
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
^~~~~
drivers/spi/mxc_spi.c:232:32: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
_func_, bitlen, (u32)dout, (u32)din);
^
include/log.h:135:26: note: in definition of macro ‘debug_cond’
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
^~~~~
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 4 Jan 2019 09:10:20 +0000 (09:10 +0000)]
imx: Fix potential lmb memory overwritten by stack
At default, u-boot reserves the memory from SP - 4KB to DRAM end for
lmb in arch_lmb_reserve. So lmb won't allocate any memory from it.
But we found the 4K gap for SP is not enough now, because some FDT
updating operations are added in our u-boot before jumping to kernel,
which needs larger stack. This causes the lmb allocated memory is overwritten
by stack.
Fix the issue by implementing the board_lmb_reserve to reserve from
SP - 16KB to memory end for lmb.
Ye Li [Fri, 4 Jan 2019 09:08:26 +0000 (09:08 +0000)]
pinctrl: imx: Fix select input issue
The pinctrl supports to set any bit in input register on iMX6 if
the MSB of input value is 0xff. But the driver uses signed int for
input value, so when executing the codes below, it won't meet.
Because this is arithmetic right shift.
if (input_val >> 24 == 0xff)
Fix the issue by changing the input_val, config_val and mux_mode to u32.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 21 Dec 2018 06:21:34 +0000 (06:21 +0000)]
imx8qxp: mek: default enable SPL
Enable SPL for i.MX8QXP MEK, and currently use SPL FIT.
The SPL enable SPL_DM to use MMC/PINCTRL/POWER DOMAIN/CLK.
Note: SPL FIT could not support secure boot chain, because i.MX8/8X
only support i.MX container format. This container format has
not been upstreamed, so we use FIT for now. When SPL container
supported, we could switch to that.
Peng Fan [Fri, 21 Dec 2018 06:21:26 +0000 (06:21 +0000)]
dts: imx8qxp-mek: introduce u-boot dtsi
Introduce u-boot dtsi for i.MX8QXP MEK board.
we do not introduce a common dtsi for SoC, because different board
has different requirement on which needs to be enabled in SPL DM.
Peng Fan [Fri, 21 Dec 2018 06:21:15 +0000 (06:21 +0000)]
imx8: scu: use dedicated MU for SPL
SPL runs in EL3 mode, except MU0_A, others are not powered on,
and could not be used. However normal U-Boot use MU1_A, so we
could not reuse the one in dts. And we could not replace the one
in dts with MU0_A, because MU0_A is reserved in secure world.
projects / u-boot.git / log