which caused part_init to be called when it was not previously.
Without this patch, the following happens when a USB sd card reader is used.
=> usb start
starting USB...
USB0: Port not available.
USB1: USB EHCI 1.00
scanning bus 1 for devices... 3 USB Device(s) found
scanning usb for storage devices... Device NOT ready
Request Sense returned 02 3A 00
### ERROR ### Please RESET the board ###
Eddie Cai [Thu, 6 Apr 2017 03:37:04 +0000 (11:37 +0800)]
usb: dwc2: invalidate the dcache before starting the DMA
We should invalidate the dcache before starting the DMA. In case there are
any dirty lines from the DMA buffer in the cache, subsequent cache-line
replacements may corrupt the buffer in memory while the DMA is still going on.
Cache-line replacement can happen if the CPU tries to bring some other memory
locations into the cache while the DMA is going on.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Reviewed-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Philipp Tomsich [Thu, 6 Apr 2017 14:58:53 +0000 (16:58 +0200)]
usb: dwc3: gadget: make cache-maintenance on event buffers more robust
Merely using dma_alloc_coherent does not ensure that there is no stale
data left in the caches for the allocated DMA buffer (i.e. that the
affected cacheline may still be dirty).
The original code was doing the following (on AArch64, which
translates a 'flush' into a 'clean + invalidate'):
# during initialisation:
1. allocate buffers via memalign
=> buffers may still be modified (cached, dirty)
# during interrupt processing
2. clean + invalidate buffers
=> may commit stale data from a modified cacheline
3. read from buffers
This could lead to garbage info being written to buffers before
reading them during even-processing.
To make the event processing more robust, we use the following sequence
for the cache-maintenance:
# during initialisation:
1. allocate buffers via memalign
2. clean + invalidate buffers
(we only need the 'invalidate' part, but dwc3_flush_cache()
always performs a 'clean + invalidate')
# during interrupt processing
3. read the buffers
(we know these lines are not cached, due to the previous
invalidation and no other code touching them in-between)
4. clean + invalidate buffers
=> writes back any modification we may have made during event
processing and ensures that the lines are not in the cache
the next time we enter interrupt processing
Note that with the original sequence, we observe reproducible
(depending on the cache state: i.e. running dhcp/usb start before will
upset caches to get us around this) issues in the event processing (a
fatal synchronous abort in dwc3_gadget_uboot_handle_interrupt on the
first time interrupt handling is invoked) when running USB mass
storage emulation on our RK3399-Q7 with data-caches on.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Thu, 6 Apr 2017 14:58:52 +0000 (16:58 +0200)]
usb: dwc3: ensure consistent types for dwc3_flush_cache
The dwc3_flush_cache() call was declared and used inconsistently:
* The declaration assumed 'int' for addresses (a potential issue
when running in a LP64 memory model).
* The invocation cast the address to 'long'.
This change ensures that both the declaration and usage of this
function consistently uses 'uintptr_t' for correct behaviour even
when the allocated buffers (to be flushed) reside outside of the
lower 32bits of memory.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Felipe Balbi [Wed, 22 Feb 2017 15:12:40 +0000 (17:12 +0200)]
usb: gadget: g_dnl: only set iSerialNumber if we have a serial#
We don't want to claim that we support a serial number string and
later return nothing. Because of that, if g_dnl_serial is an empty
string, let's skip setting iSerialNumber to a valid number.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Felipe Balbi [Wed, 22 Feb 2017 15:12:39 +0000 (17:12 +0200)]
usb: gadget: g_dnl: hold maximum string descriptor
A USB String descriptor can be up to 255 characters long and it's not
NULL terminated according to the USB spec. This means our
MAX_STRING_SERIAL should be 256 (to cope with NULL terminator).
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Kever Yang [Fri, 10 Mar 2017 04:05:14 +0000 (12:05 +0800)]
usb: dwc2: add support for external vbus supply
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Simon Glass <sjg@chromium.org>
arm: socfpga: sr1500 use environment in common header
This removes the default environment from the sr1500 header
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
This board has no upstream devicetree in the kernel source,
so set to socfpga_cyclone5_sr1500.dtb.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
- set devicetree name to match socfpga_{fpga model}_{board model}.dts
pattern
arm: socfpga: Socrates use environment in common header
This removes the default environment from the socrates headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
arm: socfpga: SoCKit use environment in common header
This removes the default environment from the SoCKit headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
arm: socfpga: DE1 use environment in common header
This removes the default environment from the de1 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
This board does not have a devicetree in the upstream kernel
source so set devicetree to socfpga_cyclone5_de1_soc.dtb.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
--
Changes in V2:
- Remove unneeded CONFIG_BOOTFILE
- set devicetree name to match socfpga_{fpga model}_{board model}.dts
pattern
arm: socfpga: C5 SoCDK use environment in common header
This removes the default environment from the C5 SoCDK headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
In addition to the above, add support to boot from the custom
a2 type partition.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
arm: socfpga: A5 SoCDK use environment in common header
This removes the default environment from the A5 socdk headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
Add support to boot from the custom a2 type partition.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v3:
- Fix small typo in defconfig, missing "C"
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
- Fix dtb name
arm: socfpga: DE0 use environment in common header
This removes the default environment from the de0 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
In addition to the above, add support to boot from the custom
a2 type partition
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
arm: socfpga: Add distro boot to socfpga common header
This adds a common environment and support for distro boot
in the common socfpga header.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v5:
- Per Frank, to support OpenSuse the ENV must be after the GPT
Changes in v4:
- Move env back to being right after the MBR
Changes in v3:
- fix spacing between asterix
- remove verify=n as a default setting
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE and fdt_addr
- cleanup spacing in MMC env size
Chee, Tien Fong [Wed, 29 Mar 2017 03:49:16 +0000 (11:49 +0800)]
ARM: socfpga: boot0 hook: remove macro from boot0 header file
Commit ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole
header file") miss out cleaning macro in this header file, and this
has broken implementation of a boot header capability in socfpga
SPL. Remove the macro in this file, and recovering it back
to proper functioning.
With the port C enabled, we can read the GPI input state of:
* the DIP switches (USER_DIPSW_HPS[3:0]/HPS_GPI[7:4])
* the push buttons (USER_PB_HPS[3:0]/HPS_GPI[11:8])
Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Signed-off by: Sid-Ali Teir <git.syedelec@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Marek Vasut <marex@denx.de>
Stephen Arnold [Fri, 24 Mar 2017 01:58:08 +0000 (18:58 -0700)]
ARM: socfpga: add fpga build and bsp handoff instructions to readme
This patch adds the steps to manually (re)build a Quartus FPGA project,
generate the required BSP glue, and update u-boot handoff files for
mainline SPL support. Requires Quartus toolchain and current U-Boot.
Signed-off-by: Steve Arnold <stephen.arnold42@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
Alex Deymo [Sun, 2 Apr 2017 08:24:34 +0000 (01:24 -0700)]
mmc: sdhci: Wait for SDHCI_INT_DATA_END when transferring.
sdhci_transfer_data() function transfers the blocks passed up to the
number of blocks defined in mmc_data, but returns immediately once all
the blocks are transferred, even if the loop exit condition is not met
(bit SDHCI_INT_DATA_END set in the STATUS word).
When doing multiple writes to mmc, returning right after the last block
is transferred can cause the write to fail when sending the
MMC_CMD_STOP_TRANSMISSION command right after the
MMC_CMD_WRITE_MULTIPLE_BLOCK command, leaving the mmc driver in an
unconsistent state until reboot. This error was observed in the rpi3
board.
This patch waits for the SDHCI_INT_DATA_END bit to be set even after
sending all the blocks.
Test: Reliably wrote 2GiB of data to mmc in a rpi3.
Signed-off-by: Alex Deymo <deymo@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
The linux kernel driver for this module does not use a delay when
writing to the SDHCI_BUFFER register. This patch mimics that behavior
in order to speed up the mmc writes on the Raspberry Pi.
Signed-off-by: Alex Deymo <deymo@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Thu, 13 Apr 2017 02:29:22 +0000 (10:29 +0800)]
mmc: gen_atmel_mci: add driver model support for mci
Add the driver model support for Atmel mci while retaining the
existing legacy code. This allows the driver to support boards
that have converted to driver model as well as those that have not.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Carlo Caione [Wed, 12 Apr 2017 18:30:42 +0000 (20:30 +0200)]
mmc: meson: add MMC driver for Meson GX (S905)
This driver implements MMC support on Meson GX (S905) based systems.
It's based on Carlo Caione's work, changes:
- BLK support added
- general refactoring
Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Tested-by: Vagrant Cascadian <vagrant@debian.org>
Wenyou Yang [Thu, 13 Apr 2017 02:31:20 +0000 (10:31 +0800)]
board: sama5d4ek: clean up code
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Wenyou Yang [Thu, 13 Apr 2017 02:31:19 +0000 (10:31 +0800)]
board: sama5d4ek: update to support DM/DT
Update the configuration files to support the device tree and driver
model, so do SPL. The device clock and pins configuration are handled
by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Wenyou Yang [Thu, 13 Apr 2017 02:31:17 +0000 (10:31 +0800)]
board: sama5d4_xplained: clean up code
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Wenyou Yang [Thu, 13 Apr 2017 02:31:16 +0000 (10:31 +0800)]
board: sama5d4_xplained: update to support DM/DT
Update the configuration files to support the device tree and
driver model, so do SPL. The device clock and pins configuration
are handled by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Wenyou Yang [Fri, 24 Mar 2017 03:34:06 +0000 (11:34 +0800)]
ARM: at91: lds: use "_image_binary_end" for DT location
The MMC SPL locates the BSS section to a different memory region
from text, then use "_image_binary_end" variable to point to the
correct device tree location.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang [Fri, 24 Mar 2017 01:18:44 +0000 (09:18 +0800)]
ARM: dts: at91: add dts file for sama5d4ek
Add the device tree file for sama5d4ek board.
The dts file is copied from Linux-4.4, do the following changes.
- add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
- fix the compilation warning.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang [Fri, 24 Mar 2017 01:18:43 +0000 (09:18 +0800)]
ARM: dts: at91: add dts files for sama5d4 Xplained
Add the device tree files for sama5d4 Xplained board.
The dts files are copied from Linux-4.4, do the following changes.
- add reg property for pinctrl node.
- move the gpio nodes(pioA, pioB, pioC ...) from the pinctrl child's
nodes to its slibling nodes.
- add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
- fix the compilation warnings.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang [Fri, 24 Mar 2017 01:18:42 +0000 (09:18 +0800)]
ARM: at91: dt: add dts file for sama5d3 Xplained
Add the device tree file for sama5d3 Xplained board.
The dts files are copied from the Linux-4.9, do changes as below.
- add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
- fix the compile warning.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang [Fri, 24 Mar 2017 01:18:41 +0000 (09:18 +0800)]
ARM: at91: dt: add dts files for sama5d3xek board
Add the device tree files for sama5d3xek board.
The dts files are copied from Linux-4.9, do the changes as below.
- add reg property for the pinctrl node.
- move the gpio nodes (pioA, pioB, pioC ...) as the pinctrl's
slibling nodes.
- add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
- fix the compile warning.
- add spi0 node aliases.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang [Thu, 23 Mar 2017 04:44:37 +0000 (12:44 +0800)]
pinctrl: at91: add pinctrl driver
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.
Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Thu, 23 Mar 2017 04:55:21 +0000 (12:55 +0800)]
mtd: nand: atmel: use another functions to set gpio value
Because there isn't the implementation of gpio_set/get_value()
and gpio_set/get_value() after the at91 gpio driver is converted
to support the driver model, use at91_set_gpio_value() and
at91_get_gpio_value()
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Thu, 23 Mar 2017 04:55:20 +0000 (12:55 +0800)]
ARM: at91: gpio: fix at91_set_gpio_value() define
When the CONFIG_ATMEL_LEGACY is undefined, according to the following
defines, at91_set_gpio_value() references to at91_set_pio_value(x, y)
with two parameters.
#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y)
#define at91_get_gpio_value(x) at91_get_pio_value(x)
But there isn't the implementation of at91_set_pio_value(x, y) with
two parameters in U-Boot. This is an error.
Same as at91_get_gpio_value(x) define.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Not force to use python from PATH. Issue was noted when building with
Yocto, because python from the distro is always taken instead of
python-native built during Yocto process.
Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 4 Apr 2017 19:00:19 +0000 (13:00 -0600)]
dm: core: Ensure DMA regions start up with the cache clean
There is a strange interaction with drivers which use DMA if the cache
starts off in a dirty state. Buffer space which the driver reads (but has
not previously written) can contain zero bytes from alloc_priv(). This can
cause corruption of the memory used by DMA for incoming data.
Fix this and add a comment to explain the problem.
This allows the dwc2 driver to work correctly with driver model, for
example.
core/uclass: Print name of device in uclass_find_device_by_seq()
uclass_find_device_by_seq() prints seq and req_seq when debugging is
enabled, but this information is not very useful by itself. Add the
name of he driver to this information. This improves debugging as it
shows which devices are being considered.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Acked-by: Simon Glass <sjg@chromium.org>
With Python 3.5.2 encode will throw an exception if val is a byte array.
Decode it to a string first. This assumes it's utf-8, if it's not valid
utf-8 it will throw an exception.
Signed-off-by: George McCollister <george.mccollister@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
os.read() returns a byte array in Python 3.5.2 and needs to be converted
into a string. Check if the returned value is an instance of bytes and
if it is decode it as a utf-8 string. If it is not a utf-8 encoded string
the decoding may fail with an exception.
Prior to this fix the comparisions check data == "" would fail when data
was b'' and would cause an infinite memory leaking loop. joins would
also fail with an exception below but due to the infinite loop it never
made it that far.
Signed-off-by: George McCollister <george.mccollister@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
serial: ns16550: Link in the DM driver when when using platdata
Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA.
This is inconsistent with the majority of other drivers. This also
blocks OF_PLATDATA boards with an 16550-compatible serial from using
serial in SPL.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 12 Apr 2017 20:41:00 +0000 (16:41 -0400)]
sandbox: Change CONFIG_SANDBOX_BITS_PER_LONG to hard-coded
Instead of having CONFIG_SANDBOX_BITS_PER_LONG in sandbox.h set to 64
with a comment to change to 32 on a 32bit host, simply set this to 64 in
asm/types.h and have the comment be there.
Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
Vignesh R [Mon, 10 Apr 2017 06:53:22 +0000 (12:23 +0530)]
tiny-printf: Add support for %p format
Add support for %p, %pa[p], %pM, %pm and %pI4 formats to tiny-printf.
%pM and %pI4 are widely used by SPL networking stack and is required if
networking support is desired in SPL.
%p, %pa and %pap are mostly used by debug prints and hence supported
only when DEBUG is enabled.
Before this patch:
$ size spl/u-boot-spl
text data bss dec hex filename
99325 4899 218584 322808 4ecf8 spl/u-boot-spl
After this patch (with CONFIG_SPL_NET_SUPPORT):
$ size spl/u-boot-spl
text data bss dec hex filename
99666 4899 218584 323149 4ee4d spl/u-boot-spl
So, this patch adds ~350 bytes to code size.
If CONFIG_SPL_NET_SUPPORT is not enabled, this adds ~25 bytes.
If CONFIG_USE_TINY_PRINTF is disabled then:
$ size spl/u-boot-spl
text data bss dec hex filename
101116 4899 218584 324599 4f3f7 spl/u-boot-spl
So, there is still ~1.4K space saved even with support for %pM/%pI4.
Compiler used is to build is:
arm-linux-gnueabihf-gcc (Linaro GCC 6.2-2016.11) 6.2.1 20161016
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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has identified this incoming email as possible spam. The original
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Content preview: Previous change to create _printch causes the stack to be
used, breaking printch before stack is available. Inline _printch to prevent
this happening. Signed-off-by: Tim Chick <tim.chick@mediatek.com> --- [...]
pts rule name description
---- ---------------------- --------------------------------------------------
0.7 RCVD_IN_XBL RBL: Received via a relay in Spamhaus XBL
[188.29.165.105 listed in zen.spamhaus.org]
3.6 RCVD_IN_PBL RBL: Received via a relay in Spamhaus PBL
1.6 RCVD_IN_BRBL_LASTEXT RBL: No description available.
[188.29.165.105 listed in bb.barracudacentral.org]
0.4 RDNS_DYNAMIC Delivered to internal network by host with
dynamic-looking rDNS
Previous change to create _printch causes the stack to be used,
breaking printch before stack is available. Inline _printch to
prevent this happening.
fw_env_open allocates buffers to store the environment, but these
buffers are never freed. This becomes quite nasty using the fw_ tools as
library, because each access to the environment (even just reading a
variable) generates a memory leak equal to the size of the environment.
Fix this renaming fw_env_close() as fw_env_flush(), because the function
really flushes the environment from RAM to storage, and add a
fw_env_close function to free the allocated resources.
Changes in the environment library are difficult to tracked by programs
using the library. Add simply an API version number that must be
increased each time when the API is changed.
This can be detected and a program can work with different versions of
the library.
Move U-Boot private data into a separate file. This
lets export fw_env.h to be used by external programs
that want to change the environment using the library
built in tools/env.
aes.h is a too generic name if this file can
be exported and used by a program.
Rename it to avoid any conflicts with
other files (for example, from openSSL).
Adam Ford [Fri, 7 Apr 2017 15:25:34 +0000 (10:25 -0500)]
imx: i.mx6q: add the initial support for LogicPD i.MX6Q SOM
Logic PD has an i.MX6Q system on module (SOM) with a development kit. The
SOM has a built-in microSD socket, DDR and NAND flash. The development kit
has an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
This have been verified to boot the i.MX6Q version over either SD
on the development kit or NAND built into the SOM. Items in the dtsi file
are specific to the SOM itself. Items in the dts file are in the baseboard.
Future versions of the SOM will come out supporting the same basebord and
potentially future base boards will come out supporting the same SOM.
Yung-Ching LIN [Tue, 28 Mar 2017 17:51:25 +0000 (01:51 +0800)]
board: advantech: dms-ba16: apply the proper register setting to fix the voltage peak issue
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: Ken Lin <yungching0725@gmail.com> Acked-by: Akshay Bhat <akshay.bhat@timesys.com>
Yung-Ching LIN [Tue, 28 Mar 2017 17:51:22 +0000 (01:51 +0800)]
board: advantech: dms-ba16: Add the configuration options for display initialization
Add the configuration options for display initialization in case we need to
do the display initialization in kernel to support different timing settings
Signed-off-by: Ken Lin <yungching0725@gmail.com> Acked-by: Akshay Bhat <akshay.bhat@timesys.com>
ARCv2: SLC: Make sure busy bit is set properly on SLC flushing
As reported in STAR 9001165532, an SLC control reg read (for checking
busy state) right after SLC invalidate command may incorrectly return
NOT busy causing software to NOT spin-wait while operation is underway.
(and for some reason this only happens if L1 cache is also disabled - as
required by IOC programming model)
Suggested workaround is to do an additional Control Reg read, which
ensures the 2nd read gets the right status.
Stefan Agner [Wed, 29 Mar 2017 19:41:23 +0000 (12:41 -0700)]
libfdt: fix build with Python 3
For some reason Python 3 seems to think it does not need to build
the library. Using the --force parameter makes sure that the library
gets built always. This is especially important since we move the
library in the next step of the Makefile, hence forcing a rebuild
every time the higher level Makefile triggers a rebuild is required
to make sure the library is always there.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Simon Glass <sjg@chromium.org>
Joel Stanley [Sun, 9 Apr 2017 18:33:58 +0000 (20:33 +0200)]
Makefile: Fix linking with modern binutils
Since Binutils 1a9ccd70f9a7[1] u-boot will not link targets that set
CONFIG_SYS_TEXT_BASE=0 with the following error:
LD u-boot
arm-linux-gnueabi-ld.bfd: u-boot: Not enough room for program headers, try
linking with -N
arm-linux-gnueabi-ld.bfd: final link failed: Bad value
The issue can be reproduced with the bad binutils and the rock2_defconfig
target.
This issue was also encountered by the powerpc kernel[2], with the fix
being to pass --no-dynamic-linker for linkers newer than 2.26 when this
flag was introduced. The option tells ld that the PIE or shared lib does
not need loaded program headers.
Ubuntu Zesty's Binutils 2.27.51.20161202 hits this error.
Signed-off-by: Joel Stanley <joel@jms.id.au>
[AF: Apply to LDFLAGS_$(SPL_BIN) as well, suggested by Tom Rini] Signed-off-by: Andreas Färber <afaerber@suse.de>
Andy Shevchenko [Sat, 1 Apr 2017 13:21:34 +0000 (16:21 +0300)]
x86: Introduce minimal PMU driver for Intel MID platforms
This simple PMU driver allows to tyrn power on and off for selected
devices. In particularly Intel Tangier needs to power on SDHCI
controllers in order to access to them during board initialization.
In the future it might be expanded to cover other Intel MID platforms,
that's why it's located under arch/x86/lib and called pmu.c.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Felipe Balbi [Sat, 1 Apr 2017 13:21:33 +0000 (16:21 +0300)]
x86: Add SCU IPC driver for Intel MID platforms
Intel MID platforms have few microcontrollers inside SoC, one of them
is so called System Controller Unit (SCU).
Here is the driver to communicate with microcontroller.
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Simon Glass <sjg@chromium.org>
Andy Shevchenko [Tue, 28 Feb 2017 12:04:10 +0000 (14:04 +0200)]
serial: Add serial driver for Intel MID
Add a specific serial driver for Intel MID platforms.
It has special fractional divider which can be programmed via UART_PS,
UART_MUL, and UART_DIV registers.
The UART clock is calculated as
UART clock = XTAL * UART_MUL / UART_DIV
The baudrate is calculated as
baud rate = UART clock / UART_PS / DLAB
Initialize fractional divider correctly for Intel Edison platform.
For backward compatibility we have to set initial DLAB value to 16
and speed to 115200 baud, where initial frequency is 29491200Hz, and
XTAL frequency is 38.4MHz.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
projects / u-boot.git / log