Remove the unneeded emmc_phy_init now that the no-inverter flag is
handled correctly after commit 2321a991bbb5 ("rockchip: sdhci: rk3568:
bypass DLL when clk <= 52 MHz").
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:24 +0000 (16:46 +0000)]
mmc: sdhci: Set UHS Mode Select field for UHS SDR25 mode
Set correct UHS Mode Select field value for UHS SDR25 (50MHz) mode.
Fixes: d1c0a2200afb ("mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Thu, 13 Apr 2023 14:13:03 +0000 (09:13 -0500)]
ARM: dts: rockchip: rk3588s-u-boot: Add rng node
Add a node for the trng found on RK3588 SoCs.
Changes in V3:
- Added Reviewed-By tag.
Changes in V2:
- None
Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Chris Morgan [Thu, 13 Apr 2023 14:13:02 +0000 (09:13 -0500)]
rockchip: rng: add trngv1 for rk3588
This adds support for the TRNG found in the RK3588 SoC to the
rockchip_rng driver so that it can be used for things such as
seeding randomness to Linux.
Changes in V3:
- Moved notes from commit to cover letter.
- Added Reviewed-By tag.
Changes in V2:
- Modified Kconfig to note that the Rockchip RNG driver supports all
versions of the hardware (v1, v2, and the trng in the rk3588).
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 17 Apr 2023 19:07:25 +0000 (19:07 +0000)]
clk: rockchip: rk3568: Add dummy I2S1_MCLKOUT_TX clock support
A RK3568 device tree pmic node can reference the I2S1_MCLKOUT_TX clock
in assigned-clocks, add dummy support to set parent of this clock to the
rk3568 cru driver.
Fixes probe of pmic driver and missing regulators on affected boards,
rk3568-evb and rk3568-rock-3a.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 17 Apr 2023 19:07:23 +0000 (19:07 +0000)]
pinctrl: rockchip: Fix IO mux selection on RK3568
IO mux selection is not working correctly for all pins. Sync mux route
data from linux to add any missing and update wrong trigger pins to fix
this. Also apply the pull-up fix needed for GPIO0 D3-D6.
Jonas Karlman [Mon, 17 Apr 2023 19:07:21 +0000 (19:07 +0000)]
rockchip: rk3588: Sync sdmmc node from linux-next
Sync the sdmmc node from linux-next, include required nodes in SPL and
imply Kconfig options required for functional sdmmc clk in SPL and
U-Boot proper.
This make it possible for both SPL and U-Boot proper to configure sdmmc
clocks. In SPL, before TF-A is loaded, scru regs is configured, in
U-Boot proper a SCMI message is sent to TF-A.
Fixes: 95c8656b72dc ("ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 17 Apr 2023 19:07:20 +0000 (19:07 +0000)]
rockchip: rk3588: Add support for sdmmc clocks in SPL
Booting from sdmmc on RK3588 currently works because of a workaround in
the device tree, clocks are reordered so that the driver use ciu-sample
instead of ciu, and the BootRom initializes sdmmc clocks before SPL is
loaded into DRAM.
The sdmmc clocks are normally controlled by TF-A using SCMI. However,
there is a need to control these clocks in SPL, before TF-A has started.
This adds a rk3588_scru driver to control the sdmmc clocks in SPL before
TF-A has started, using scru regs. It also adds a small glue driver to
bind the scmi clock node to the rk3588_scru driver in SPL.
Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 17 Apr 2023 19:07:18 +0000 (19:07 +0000)]
clk: scmi: Add Kconfig option for SPL
Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options
enabled and SPL_FIRMWARE disabled result in the following error.
drivers/clk/clk_scmi.o: in function `scmi_clk_gate':
drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate':
drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate':
drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_probe':
drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel'
make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
make: *** [Makefile:2043: spl/u-boot-spl] Error 2
Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 17 Apr 2023 19:07:15 +0000 (19:07 +0000)]
rockchip: rk35xx: Fix boot with a large fdt blob
The TF-A blobs used to boot RK3568 and RK3588 boards is based on atf
v2.3. Mainline atf v2.3 contains an issue that could lead to a crash
when it fails to parse the fdt blob being passed as the platform param.
An issue that was fixed in atf v2.4.
The vendor TF-A seem to suffer from a similar issue, and this prevents
booting when fdt blob is large enough to trigger this condition.
Fix this by implying SPL_ATF_NO_PLATFORM_PARAM to let u-boot pass a
NULL pointer instead of the fdt blob as the platform param.
This fixes booting Radxa ROCK 3A after recent sync of device tree.
Fixes: 073d911ae64a ("rockchip: rk3568-rock-3a: Sync device tree from linux") Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Jonas Karlman [Mon, 17 Apr 2023 19:07:14 +0000 (19:07 +0000)]
rockchip: rk3588-rock-5b: Fix sdmmc boot
Running U-Boot from a SD-card on ROCK 5 Model B fails to load atf using
DMA and prints debug_uart messages.
<debug_uart>
<debug_uart>
U-Boot SPL 2023.04-rc3 (Mar 12 2023 - 00:30:16 +0000)
Trying to boot from MMC1
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-1' image node
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Use fifo-mode to disable DMA in SPL, add same-as-spl to boot-order and
remove DEBUG_UART_ANNOUNCE option to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
John Keeping [Mon, 27 Mar 2023 11:01:10 +0000 (12:01 +0100)]
rockchip: otp: fix misc_read() return values
The documentation for misc_read() says:
Return: number of bytes read if OK (may be 0 if EOF), -ve on error
The Rockchip efuse driver implements this so it should return the number
of bytes read rather than zero on success. Fix this so that the driver
follows the usual contract for read operations.
Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
John Keeping [Mon, 27 Mar 2023 11:01:09 +0000 (12:01 +0100)]
rockchip: efuse: fix misc_read() return values
The documentation for misc_read() says:
Return: number of bytes read if OK (may be 0 if EOF), -ve on error
The Rockchip efuse driver implements this so it should return the number
of bytes read rather than zero on success. Fix this so that the driver
follows the usual contract for read operations.
Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
John Keeping [Mon, 27 Mar 2023 11:01:08 +0000 (12:01 +0100)]
rockchip: misc: fix misc_read() return check
misc_read() is documented to return the number of bytes read or a
negative error value. The Rockchip drivers currently do not implement
this correctly and instead return zero on success or a negative error
value.
In preparation for fixing the drivers, fix the condition here to only
error on negative values.
Suggested-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Fri, 24 Mar 2023 18:53:07 +0000 (13:53 -0500)]
rockchip: video: Add support for RK3568 DSI Host
Add support for DSI Host controller on Rockchip RK3568. This driver
is heavily based on the Rockchip dw_mipi_dsi_rockchip.c driver in
Linux and the stm32_dsi.c driver in U-Boot. It should be easy to add
support for other SoCs as the only missing component from the mainline
driver is setting the VOP big or VOP little (which the rk3568 does
not have).
Driver was tested for use in sending commands to a DSI panel in order
to obtain the panel ID.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Fri, 24 Mar 2023 18:53:06 +0000 (13:53 -0500)]
drivers: phy: add Innosilicon DSI-DPHY driver
Add support for the Innosilicon DSI-DPHY driver for Rockchip SOCs.
The driver was ported from Linux and tested on a Rockchip RK3566
based device to query the panel ID via a DSI command.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add missing high row detection so that U-Boot TPL prints Row=16, same as
the Rockchip ddr init bin:
"BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB"
Signed-off-by: Jonathan Liu <net147@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 19 Mar 2023 18:39:51 +0000 (18:39 +0000)]
gpio: rockchip: Add support for RK3568 and RK3588 banks
The GPIO V2 controller on RK3568 and RK3588 works very similar to
prior generation, main difference is the use of a write mask in the
upper 16 bits and register address offset have changed.
GPIO_VER_ID is a new register at 0x0078 that is used to determine when
the driver should use new or old register offsets and values. Earlier
generation return 0x0 from this offset.
Refactor code and add support for the GPIO V2 controller used in RK3568
and RK3588.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Currently the Rockchip rk3066a u-boot-tpl.bin file needs
to add the characters "RK30", while the other SoCs replace
the first 4 bytes. Bring this in line with the rest by
lowering CONFIG_TPL_TEXT_BASE and update rockchip.rst
instructions.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Sun, 19 Mar 2023 15:05:57 +0000 (16:05 +0100)]
arm: dts: rockchip: sync rk3066/rk3188 DT files from linux-next v6.2-rc4
Sync rk3066/rk3188 DT files from Linux.
This is the state as of linux-next v6.2-rc4.
New nfc node for MK808 rk3066a.
CRU nodes now have a clock property.
To prefend dtoc errors a fixed clock must also be
included for tpl/spl in the rk3xxx-u-boot.dtsi file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The gpio node names are made generic, but without
gpio bank ID. Add gpio-ranges to rk3066a-u-boot.dtsi
for now till a better method is found.
Disable gpio6 as the driver gives an error code
on return as status.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Sun, 19 Mar 2023 15:02:18 +0000 (16:02 +0100)]
rockchip: gpio: rk_gpio: use ROCKCHIP_GPIOS_PER_BANK as divider
The current divider to calculate the bank ID can change.
Given the Rockchip TRM not all gpio-banks have 32 pins per bank.
The "gpio-ranges" syntax allows multiple items with variable number
of pins. Use a constant ROCKCHIP_GPIOS_PER_BANK as fixed divider.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Wed, 15 Mar 2023 18:34:13 +0000 (19:34 +0100)]
clk: rockchip: clk_rk3288: add PCLK_RKPWM
The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM
instead of PCLK_PWM. They have the same pclk_cpu parent,
so add PCLK_RKPWM to rk3288_clk_get_rate().
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the vop/lvds/mipi/hdmi nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Wed, 15 Mar 2023 18:33:50 +0000 (19:33 +0100)]
arm: dts: rockchip: rk3288: partial sync edp node
The rk3288 edp node has a phy node in Linux with a clock
property while current U-Boot driver expects this clock
on position index 1. Move U-Boot-specific DT clock properties
to rk3288-u-boot.dtsi and partially sync the edp node.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In the current rk3288.dtsi file the compatible string for
the DisplayPort(DP) node ends with "edp". The string in the
binding ends with "dp" which conflicts with "cdn-dp" as a
search term. Add "rk3288-dp" as compare string to select
vop_id.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Wed, 15 Mar 2023 18:33:25 +0000 (19:33 +0100)]
arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the grf and pmu nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Wed, 15 Mar 2023 18:31:57 +0000 (19:31 +0100)]
arm: dts: rockchip: rk3288: move io-domains nodes
In order to better compare the Linux rk3288.dtsi version
with the U-Boot version move the io-domains nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: John Keeping <john@metanate.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jianqun Xu [Wed, 15 Mar 2023 15:32:15 +0000 (17:32 +0200)]
pinctrl: rockchip: support rk3588 pinctrl
Add support for Rockchip rk3588 variant of pinctrl.
The driver is adapted from the Linux driver.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[eugen.hristev@collabora.com:
port to latest U-boot, bring more changes from Linux
use translated pull values table] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Jonas Karlman [Tue, 28 Feb 2023 21:38:25 +0000 (21:38 +0000)]
rockchip: Use an external TPL binary on RK3588
There is no support to initialize DRAM on RK3588 SoCs using U-Boot TPL
and instead an external TPL binary must be used to generate a bootable
u-boot-rockchip.bin image.
Enable ROCKCHIP_EXTERNAL_TPL by default for RK3588, add build steps for
RK3588 to documentation and clean up CONFIG_BINMAN_FDT options.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Jagan Teki <jagan@edgeble.ai>
Kever Yang [Thu, 2 Mar 2023 07:12:57 +0000 (15:12 +0800)]
board: rockchip: Add rk3588 evb
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for
rockchip and also a reference board for board vendors.
Hardware:
SoC: RK3588
DRAM: LPDDR4X 8GB
Debug: UART2 via USB
PCIe: 3x4 *1
SATA *2
HDMI out *2
HDMI IN *1
USB2.0 Host *2
USB3.0 Host *1
Type C *1
MIPI DSI panel
dts Sync from Linux v6.2.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@edgeble.ai>
Quentin Schulz [Wed, 1 Mar 2023 17:31:15 +0000 (18:31 +0100)]
rockchip: ringneck-px30: enforce ENV_IS_NOWHERE with Kconfig select
Instead of letting the compiler error out if CONFIG_ENV_IS_NOWHERE is
not selected by the user, let's just enforce it when the user builds for
Ringneck PX30 so that no check needs to be performed by the compiler and
the configuration is always valid.
Suggested-by: Tom Rini <trini@konsulko.com> Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 1 Mar 2023 17:31:14 +0000 (18:31 +0100)]
rockchip: puma-rk3399: enforce ENV_IS_NOWHERE with Kconfig select
Instead of letting the compiler error out if CONFIG_ENV_IS_NOWHERE is
not selected by the user, let's just enforce it when the user builds for
Puma RK3399 so that no check needs to be performed by the compiler and
the configuration is always valid.
Suggested-by: Tom Rini <trini@konsulko.com> Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.
Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.
Fix it by using MAX(mmc->tran_speed, mmc->clock)
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Marek Vasut [Mon, 20 Mar 2023 20:05:47 +0000 (21:05 +0100)]
ARM: renesas: Enable rswitch, serdes and PHY driver on R8A779F0 S4 Spider
Enable Renesas RSwitch driver, matching SERDES PHY driver and Marvell
10G ethernet PHY driver in R8A779F0 S4 Spider board configuration to
make ethernet available via the RSwitch ports.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Thu, 23 Mar 2023 00:21:28 +0000 (01:21 +0100)]
configs: m68k: Use default shell prompt
The current shell prompt '->' interferes with CI matching on 'bdinfo'
output. When CI test.py attempts to locate memory information in the
'bdinfo' output, it matches on '->' prefix which is identical to the
shell prefix. Switch the prompt to default '=>' one to avoid this
interference.
Suggested-by: Tom Rini <trini@konsulko.com> # found the CI oddity Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Phong Hoang [Mon, 20 Mar 2023 20:05:04 +0000 (21:05 +0100)]
net: rswitch: Add Renesas Ethernet Switch
This patch adds Ethernet Switch support that found on R-Car S4
(r8a779f0) SoC. This is extracted from multiple patches from
downstream BSP, with additional rework of the network device
registration.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[Marek: Rework the driver to support all ports via subdrivers.
Split the driver up, add generic PHY framework support.
Generic code clean ups.] Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Marek Vasut [Sun, 19 Mar 2023 17:09:43 +0000 (18:09 +0100)]
phy: renesas: Add Renesas Ethernet SERDES driver for R-Car S4-8
Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0).
The datasheet describes initialization procedure without any information
about registers' name/bits. So, this is all black magic to initialize
the hardware. Especially, all channels should be initialized at once.
This driver is imported and adjusted from Linux 6.3-rc1 commit: 50133cd3e8dd1 ("phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
colibri-imx6ull: specify MTD partitions on command line
Disable fdt_fixup_mtdparts() and pass MTD partition on the command
line. Dynamically editing the fdt with a static partitions configuration
is not required and there is no advantages compared to using the command
line. This change should prevent boot failures as the one in [0].
colibri-imx7: specify MTD partitions on command line
Disable fdt_fixup_mtdparts() and pass MTD partition on the command
line. Dynamically editing the fdt with a static partitions configuration
is not required and there is no advantages compared to using the command
line. This change should prevent boot failures as the one in [0].
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
D-Link DIR-885L and DIR-890L routers, we need to explicitly
select the ECC like this in the device tree:
This is handled by the Linux kernel but U-Boot core does
not respect this. Fix it up by parsing the algorithm and
preserve the behaviour using this property to select
software BCH as far as possible.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/all/20230308212851.370939-1-linus.walleij@linaro.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Frieder Schrempf [Mon, 13 Feb 2023 09:46:24 +0000 (10:46 +0100)]
MAINTAINERS: Add entry for SPI NAND framework and drivers
In [1] Michael agreed on taking patches for SPI NAND through the RAW
NAND tree. Add a dedicated entry to the MAINTAINERS file which adds
Michael and Dario as maintainers and myself as reviewer.
Marek Vasut [Thu, 23 Mar 2023 00:22:41 +0000 (01:22 +0100)]
CI: Add m68k target
Add M5208EVBE board to CI. This does not use default config due to
limitations of QEMU emulation, instead the timer is switched from
DMA timer to PIT timer and RAMBAR accesses are inhibited.
Local QEMU launch command is as follows:
$ qemu-system-m68k -nographic -machine mcf5208evb -cpu m5208 -bios u-boot.bin
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Angelo Dureghello <angelo@kernel-space.org>
Marek Vasut [Thu, 23 Mar 2023 00:20:41 +0000 (01:20 +0100)]
arch: m68k: Add QEMU specific RAMBAR workaround
The QEMU emulation of m68k does not support RAMBAR accesses,
add Kconfig option which inhibits those accesses, so that
U-Boot can be started in m68k QEMU for CI testing purpopses
until QEMU emulation improves.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Thu, 23 Mar 2023 00:20:40 +0000 (01:20 +0100)]
arch: m68k: Introduce trivial PIT based timer
The QEMU emulation of m68k does not support DMA timer, the only
timer that is supported is the PIT timer. Implement trivial PIT
timer support for m68k.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Thu, 23 Mar 2023 00:20:39 +0000 (01:20 +0100)]
arch: m68k: Use existing CONFIG_MCFTMR instead of CFG_MCFTMR
There is an existing CONFIG_MCFTMR Kconfig symbol,
use it and drop all other instances of CFG_MCFTMR.
This duality is likely a result of bogus conversion
to Kconfig.
Fixes: 7ff7b46e6ce ("m68k: rename CONFIG_MCFTMR to CFG_MCFTMR") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tom Rini [Fri, 14 Apr 2023 14:50:04 +0000 (10:50 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
The biggest change is some refactoring of the H616 DRAM driver, which
allows better fine-tuning for each board, and is the base for pending
LPDDR3 and LPDDR4 support, needed by new boards. The sun8i-emac
Ethernet driver sees some refactoring that enables it for the Allwinner
D1 EMAC IP. The sunxi HDMI driver is now using more DT properties. Also
the early SPL code now supports some odd H616 SoC variant.
There are some more patches pending, that require the final review
touches and some testing, I will send a separate PR for them later.
The gitlab CI completed successfully, and I boot tested a few boards
with different SoCs, via FEL and SD card, into Linux.
Tony Dinh [Mon, 3 Apr 2023 04:42:33 +0000 (21:42 -0700)]
ddr: marvell: a38x: Perform DDR training sequence again for 2nd boot
- DDR Training sequence happens very fast. The speedup in boot time is
negligible by skipping the training sequence during 2nd boot or after.
So remove the check and skip.
- This change improves the robustness of DDR training. If u-boot crashed
during DDR training, the training could be left in a limbo state, where
the BootROM has recorded that it is already in a 2nd boot. The training
must be repeated in this scenario to get out of this limbo state, but due
to the check it cannot be performed.
Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Wed, 29 Mar 2023 19:25:58 +0000 (21:25 +0200)]
arm: mvebu: spl: Allow to build SATA kwbimage for 4K Native disks
Add a new config option CONFIG_MVEBU_SPL_SATA_BLKSZ for specifying block
size of SATA disk. This information is used during building of SATA
kwbimage and must be correctly set, otherwise BootROM does not load SPL.
For 4K Native disks CONFIG_MVEBU_SPL_SATA_BLKSZ must be set to 4096.
Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Pali Rohár [Wed, 29 Mar 2023 19:25:57 +0000 (21:25 +0200)]
tools: kwboot: Add support for parsing SATA images with non-512 block size
Currently kwboot expected that sector size for SATA image is always 512
bytes. If SATA image cannot be parsed with sector size of 512 bytes, try
larger sector sizes which are power of two and up to the 32 kB. Maximal
theoretical value is 32 kB because ATA IDENTIFY command returns sector size
as 16-bit number.
Pali Rohár [Wed, 29 Mar 2023 19:25:56 +0000 (21:25 +0200)]
tools: kwbimage: Add support for SATA images with non-512 byte block size
SATA kwbimage contains offsets in block size unit, not in bytes.
Until now kwbimage expected that SATA disk always have block size of 512
bytes. But there are 4K Native SATA disks with block size of 4096 bytes.
New SATA_BLKSZ command allows to specify different block size than 512
bytes and therefore allows to generate kwbimage for disks with different
block sizes.
This change add support for generating SATA images with different block
size. Also it add support for verifying and dumping such images.
Because block size itself is not stored in SATA kwbimage, image
verification is done by checking every possible block size (it is any
power of two value between 512 and 32 kB).
cmd: mvebu/bubt: a38x: Do not hardcode SATA block size to 512
Find SATA block device by blk_get_devnum_by_uclass_id() function and read
from it the real block size of the SATA disk. In case of error, fallback
back to 512 bytes.
Andre Przywara [Thu, 8 Dec 2022 20:38:54 +0000 (20:38 +0000)]
sunxi: A64: drop boot0 header reservation
In the early days of the Allwinner A64 U-Boot support, we relied on a
vendor provided "boot0" binary to perform the DRAM initialisation. This
replaced the SPL, and required to equip the U-Boot (proper) binary with
a vendor specific header to be recognised as a valid boot0 payload.
Fortunately these days are long gone (we gained SPL and DRAM support in
early 2017!), and we never needed to use that hack on any later 64-bit
Allwinner SoC.
Since this is highly obsolete by now, remove that option from the
defconfigs of all A64 boards. We leave the code still in here for now,
since some people expressed their interest in this.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Wed, 5 Apr 2023 20:30:11 +0000 (21:30 +0100)]
sunxi: arm64: boot0.h: runtime check for RVBAR address
Some SoCs of the H616 family use a die variant, that puts some CPU power
and reset control registers at a different address. There are examples
of two instances of the same board, using different die revisions of the
otherwise same H313 SoC. We need to write to a register in that block
*very* early in the SPL boot, to switch the core to AArch64.
Since the devices are otherwise indistinguishable, let the SPL code read
that die variant and use the respective RVBAR address based on that.
That is a bit tricky, since we need to do that in hand-coded AArch32
machine language, shared by all 64-bit SoCs. To avoid build dependencies
in this mess, we always provide two addresses to choose from, and just
give identical values for all other SoCs. This allows the same code to
run on all 64-bit SoCs, and controls this switch behaviour purely from
Kconfig.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
To switch the ARMv8 Allwinner SoCs into the 64-bit AArch64 ISA, we need
to program the 64-bit start code address into an MMIO mapped register
that shadows the architectural RVBAR register.
This address is SoC specific, with just two versions out there so far.
Now a third address emerged, on a *variant* of an existing SoC (H616).
Change the boot0.h start code to make this address a Kconfig
selectable option, to allow easier maintenance.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Currently twr2rd, trd2wr and twtp are constants, but according to
vendor driver they are calculated from other values. Do that here too,
in preparation for later introduction of new parameter.
While at it, introduce constant for t_wr_lat, which was incorrectly
calculated from tcl before.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
sunxi: Parameterize bit delay code in H616 DRAM driver
These values are highly board specific and thus make sense to add
parameter for them. To ease adding support for new boards, let's make
them same as in vendor DRAM settings.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
sunxi: Convert H616 DRAM options to single setting
Vendor DRAM settings use TPR10 parameter to enable various features.
There are many mores features that just those that are currently
mentioned. Since new will be added later and most are not known, let's
reuse value from vendor DRAM driver as-is. This will also help adding
support for new boards.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
While ODT values for same memory type are similar, they are not
necessary the same. Let's parameterize them and make parameter same as
in vendor DRAM settings. That way it will be easy to introduce new board
support.
Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This board is configured with CONFIG_USB1_VBUS_PIN="PH24", but no
regulator exists in its device tree. Add the regulator, so USB will
continue to work when the PHY driver switches to using the regulator
uclass instead of a GPIO.
Update the device tree here because it does not exist in Linux.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 22:51:06 +0000 (16:51 -0600)]
net: sun8i-emac: Remove the SoC variant ID
Now that all differences in functionality are covered by individual
flags, remove the enumeration of SoC variants.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 22:51:05 +0000 (16:51 -0600)]
net: sun8i-emac: Use common syscon setup for R40
While R40 puts the EMAC syscon register at a different address from
other variants, the relevant portion of the register's layout is the
same. Factor out the register offset so the same code can be shared
by all variants. This matches what the Linux driver does.
This change provides two benefits beyond the simplification:
- R40 boards now respect the RX delays from the devicetree
- This resolves a warning on architectures where readl/writel
expect the address to have a pointer type, not phys_addr_t.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 22:51:04 +0000 (16:51 -0600)]
net: sun8i-emac: Add a flag for the internal PHY switch
Describe this feature instead of using the SoC ID.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 22:51:03 +0000 (16:51 -0600)]
net: sun8i-emac: Add a flag for RMII support
Describe this feature instead of using the SoC ID.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 22:51:02 +0000 (16:51 -0600)]
net: sun8i-emac: Add a structure for variant data
Currently, EMAC variants are distinguished by their identity, but this
gets unwieldy as more overlapping variants are added. Add a structure so
we can describe the individual feature differences between the variants.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Mon, 28 Nov 2022 07:02:28 +0000 (01:02 -0600)]
video: sunxi: dw-hdmi: Use DM for HVCC regulator
The HDMI PHY depends on the HVCC supply being enabled. So far we have
relied on it being enabled by an earlier firmware stage (SPL or TF-A).
Attempt to enable the regulator here, so we can remove that dependency.
Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Samuel Holland [Mon, 28 Nov 2022 07:02:27 +0000 (01:02 -0600)]
video: sunxi: dw-hdmi: Use DM for clock gates and resets
This abstracts away the CCU register layout, which is necessary for
supporting new SoCs like H6 with a reorganized CCU. One of the resets is
referenced from the PHY node instead of the controller node, so it will
have to wait until the PHY code is factored out to a separate driver.
Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
This driver is actually used for powerpc and m68k/ColdFire.
On ColdFire SoC's, interrupt flag get not set if IIEN flag (mbcr bit6,
interrupt enabled) is not set appropriately before each transfert.
As a result, the transfert hangs forever waiting for IIEN.
This patch set IIEN before each transfert, while considering this fix
as not harming powerpc arch.
projects / u-boot.git / log