Peng Fan [Mon, 4 May 2020 14:08:53 +0000 (22:08 +0800)]
nand: mxs: correct bitflip for erased NAND page
This patch is a porting of
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/
commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
"
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.
Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
"
In this patch, i.MX6UL is added and threshold changed to use ecc_strength.
Peng Fan [Mon, 4 May 2020 14:08:52 +0000 (22:08 +0800)]
nand: mxs: fix the bitflips for erased page when uncorrectable error
This patch is porting from linux:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/
?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768
"
We may meet the bitflips in reading an erased page(contains all 0xFF),
this may causes the UBIFS corrupt, please see the log from Elie:
-----------------------------------------------------------------
[ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes
...
[ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815
[ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383
[ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383
-----------------------------------------------------------------
This patch does a check for the uncorrectable failure in the following steps:
[0] set the threshold.
The threshold is set based on the truth:
"A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH
do the ECC."
For the sake of safe, we will set the threshold with half the gf_len, and
do not make it bigger the ECC strength.
[1] count the bitflips of the current ECC chunk, assume it is N.
[2] if the (N <= threshold) is true, we continue to read out the page with
ECC disabled. and we count the bitflips again, assume it is N2.
(We read out the whole page, not just a chunk, this makes the check
more strictly, and make the code more simple.)
[3] if the (N2 <= threshold) is true again, we can regard this is a erased
page. This is because a real erased page is full of 0xFF(maybe also has
several bitflips), while a page contains the 0xFF data will definitely
has many bitflips in the ECC parity areas.
[4] if the [3] fails, we can regard this is a page filled with the '0xFF'
data.
"
Ye Li [Mon, 4 May 2020 14:08:51 +0000 (22:08 +0800)]
mtd: gpmi: provide the option to use legacy bch geometry
Provide an option in DT to use legacy bch geometry, which compatible
with the 3.10 kernel bch setting. To enable the feature, adding
"fsl,legacy-bch-geometry" under gpmi-nand node.
NOTICE: The feature must be enabled/disabled in both u-boot and kernel.
Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 4 May 2020 14:08:50 +0000 (22:08 +0800)]
mtd: gpmi: change the BCH layout setting for large oob NAND
The code change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes) and proposed a new
way to set ECC layout.
Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.
The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is
1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.
2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.
Previous code has two methods for ECC layout setting, the
legacy_calc_ecc_layout and calc_ecc_layout_by_info, the difference
between these two methods is, legacy_calc_ecc_layout set the chunk size
larger chan oob size and then set the maximum ECC strength that oob can
afford. While the calc_ecc_layout_by_info set chunk size and ECC
strength according to NAND spec. It has been proved that the first
method cannot provide safe ECC strength for some modern NAND chips, so
in current code,
1. Driver read NAND parameters first and then chose the proper ECC
layout setting method.
2. If the oob is large or NAND required data chunk larger than oob size,
chose calc_ecc_for_large_oob, otherwise use calc_ecc_layout_by_info
3. legacy_calc_ecc_layout only used for some NAND chips does not contains
necessary information. So this is only a backup plan, it is NOT
recommended to use these NAND chips.
Signed-off-by: Han Xu <b45815@freescale.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:19:55 +0000 (22:19 +0800)]
imx8mp: Set default SNSR25C for TMU probe1
So far u-boot only load SNSR25C for TMU main probe (probe 0). However,
kernel enables two probes. So it also needs to set default SNSR25C of
TCALIV1 for blank samples.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:19:54 +0000 (22:19 +0800)]
imx: load calibration parameters from fuse for i.MX8MP
i.MX8MP thermal which has two probes and supports temperature range
from -40 to 125. The driver still uses default 1p HW
calibration at 25C and loads calibration parameters from fuse.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:19:53 +0000 (22:19 +0800)]
imx: i.MX8MN: Enable loading TASR and TCALIV from fuse
Like iMX8MM, iMX8MN also needs SW to load TMU TASR and TCALIV registers
value from fuse before enabling TMU calibration. Otherwise the calibration
is not exact.
Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:19:51 +0000 (22:19 +0800)]
thermal: imx_tmu: support i.MX8MP
Support i.MX8MP thermal which has two probes and supports
temperature range from -40 to 125. Still uses default 1p HW
calibration at 25C and loads calibration parameters from fuse.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:19:50 +0000 (22:19 +0800)]
thermal: imx_tmu: Check the TEMP range for iMX8MM
On iMX8MM, the V flag in TRISTR register only reflect the state of SNSR
value, not the calibrated TEMP value. So checking this flag is not
reliable. Per IC suggestion, change to read the TEMP/AVG_TEMP directly
and check whether it in valid range 10-125C.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:19:48 +0000 (22:19 +0800)]
thermal: imx_tmu: support TMU arch level initialization
i.MX8MM TMU needs to load some registers from fuse, this is arch
dependent operation and may vary on different platforms. So add
a interface for arch level initialization.
Peng Fan [Sun, 3 May 2020 14:19:47 +0000 (22:19 +0800)]
thermal: imx_tmu: Add support for thermal sensor on iMX8MM
The analog sensors on iMX8MM are new, used for 14LPP process. So the
Temperature Sensor Monitoring Unit (TMU) has some change accordingly.
We use version 2 in TMU driver to represent the new TMU, so the one
driver can service for both i.MX8MQ/M.
Ye Li [Sun, 3 May 2020 14:41:19 +0000 (22:41 +0800)]
fec: Move imx_get_mac_from_fuse declare to imx file
imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp,
we have two different ENET controllers and both need to call this
function. So decouple its declare from fec driver.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:41:14 +0000 (22:41 +0800)]
net: Add eth phy generic driver for shared MDIO
For dual ethernet controllers, the HW design may connect ETH phys to
one MDIO ports. So two different ethernet drivers have to share MDIO bus.
Since two ethernet drivers are independent, we can't ensure their probe
order.
To resolve this problem, introduce an eth phy generic driver and uclass.
After eth-uclass binds, we search the mdio node and binds the phy node
with the eth-phy-generic driver.
When one eth driver get its phy device, the parent of phy device will
probe prior than phy device. So this ensure the eth driver ownes the
MDIO bus will be probed before using its MDIO.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 1 May 2020 14:08:34 +0000 (22:08 +0800)]
imx: add module fuse support
There are different parts from one SoC. Take i.MX6ULL for example,
some part might not have ENET, some might have; some might not have
USB, some might have. The information could be got from OCOTP,
to make one image support the different parts, we need runtime
disable linux kernel dts node and uboot driver probe if the
corresponding module not exists in the part.
Marek Vasut [Wed, 29 Apr 2020 18:09:08 +0000 (20:09 +0200)]
ARM: imx: pico-imx8mq: Add support for Technexion Pico-iMX8MQ
Add initial support for Technexion Pico-iMX8MQ SoM on PicoPI carrier
board. Currently working is ethernet, serial, eMMC. DT is imported
from Linux 5.4.28 ("462afcd6e7ea") .
test: fix naming of test functions in the log test suite
Both the nolog as well as the syslog tests were not found by Python
function generate_ut_subtest() due to not following the nameing
requirements imposed by the regular expression used to find linker
generated list entries in file u-boot.sym.
Adjust the naming of test functions.
With the patch the following tests are executed successfully for
sandbox_defconfig:
Rasmus Villemoes [Thu, 26 Mar 2020 23:02:00 +0000 (00:02 +0100)]
env/sf.c: honour CONFIG_SPL_SAVEENV
Deciding whether to compile the env_sf_save() function based solely on
CONFIG_SPL_BUILD is wrong: For U-Boot proper, it leads to a build
warning in case CONFIG_CMD_SAVEENV=n (because the initialization of
the .save member is guarded by CONFIG_CMD_SAVEENV, while the
env_sf_save() function is built if !CONFIG_SPL_BUILD - and even
without the CONFIG_CMD_SAVEENV guard, the env_save_ptr() macro would
just expand to NULL, with no reference to env_sf_save visible to the
compiler). And for SPL, when one selects CONFIG_SPL_SAVEENV, one
obviously expects to actually be able to save the environment.
The compiler warning can be fixed by using a "<something> ?
env_sf_save : NULL" construction instead of a macro that just eats its
argument and expands to NULL. That way, if <something> is false,
env_sf_save gets eliminated as dead code, but the compiler still sees
the reference to it.
For <something>, we can use CONFIG_IS_ENABLED(SAVEENV), which is true
precisely:
- For U-Boot proper, when CONFIG_CMD_SAVEENV is set (because
CONFIG_SAVEENV is a hidden config symbol that gets set if and only
if CONFIG_CMD_SAVEENV is set).
- For SPL, when CONFIG_SPL_SAVEENV is set.
As a bonus, this also removes quite a few preprocessor conditionals.
This has been run-time tested on a mpc8309-derived board to verify
that saving the environment does indeed work in SPL with these patches
applied.
Ye Li [Sun, 3 May 2020 14:27:02 +0000 (22:27 +0800)]
sata: dwc_ahsata: Fix incorrect free
Fix coverity issue CID 43665: Free of address-of expression (BAD_FREE)
incorrect_free: free frees incorrect pointer pp.
pp points the port array field of struct ahci_uc_priv, should not free it.
Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Ye Li [Sun, 3 May 2020 14:27:01 +0000 (22:27 +0800)]
sata: ahsata: Fix wrong operand for checking SERR DIAG_X
Fix coverity issue CID 3261683: Wrong operator used
(CONSTANT_EXPRESSION_RESULT) operator_confusion:
({...; __v;}) | 67108864 is always 1/true regardless of the values
of its operand. This occurs as the logical operand of !
When DIAG_X is set, the PHY COMINIT signal is detected, so
should use '&' to check whether it is set.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Mon, 4 May 2020 13:26:19 +0000 (15:26 +0200)]
treewide: mem: Remove alternate memtest setup from Mox and x530
The commit e89f8aae3d67 ("treewide: Migrate CONFIG_SYS_ALT_MEMTEST to Kconfig")
setup correct dependency on MEMTEST that's why there is no reason to enable
enable alternate memtest without mtest command.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is no real need to exactly define space for saving patterns for
alternate memory test. It is much easier to allocate space on the stack and
use it instead of trying to find out space where pattern should be saved.
For example if you want to test the whole DDR memory you can't save patter
to DDR and you need to find it out. On Xilinx devices DDR or OCM addresses
were chosen but that means that OCM needs to be mapped and U-Boot has
access permission there.
It is easier to remove this limitation and simply save it on stack because
it is very clear that memory test can't rewrite U-Boot and U-Boot has also
full access to memory where runs from.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
Since pkcs7_parse_message() returns an error pointer, we must not
check for NULL. We have to explicitly set msg to NULL in the error
case, otherwise the call to pkcs7_free_message() on the goto err
path will assume it's a valid object.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Add missing include linux/err.h Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Patrick Wildt [Thu, 7 May 2020 00:13:18 +0000 (02:13 +0200)]
efi_loader: efi_variable_parse_signature() returns NULL on error
efi_variable_parse_signature() returns NULL on error, so IS_ERR()
is an incorrect check. The goto err leads to pkcs7_free_message(),
which works fine on a NULL ptr.
Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Michael Walle [Wed, 6 May 2020 22:11:58 +0000 (00:11 +0200)]
phy: atheros: ar8035: remove static clock config
We can configure the clock output in the device tree. Disable the
hardcoded one in here. This is highly board-specific and should have
never been enabled in the PHY driver.
If bisecting shows that this commit breaks your board it probably
depends on the clock output of your Atheros AR8035 PHY. Please have a
look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
"clk-out-frequency = <125000000>" because that value was the hardcoded
value until this commit.
Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michael Walle [Wed, 6 May 2020 22:11:57 +0000 (00:11 +0200)]
phy: atheros: add device tree bindings and config
Add support for configuring the CLK_25M pin as well as the RGMII I/O
voltage by the device tree.
By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
But this output can also be changed by software to other frequencies.
This commit introduces a generic way to configure this output.
Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V.
An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V
option needs an external supply voltage. This commit adds support to
switch the internal LDO to 1.8V.
Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Vladimir Oltean [Wed, 6 May 2020 22:11:52 +0000 (00:11 +0200)]
phy: atheros: Clarify the intention of ar8021_config
Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the common
function.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Vladimir Oltean [Wed, 6 May 2020 22:11:51 +0000 (00:11 +0200)]
phy: atheros: Explicitly disable RGMII delays
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Vladimir Oltean [Wed, 6 May 2020 22:11:48 +0000 (00:11 +0200)]
phy: atheros: Make RGMII Tx delays actually configurable for AR8035
Delete the extraneous write to debug reg 5 that enables Tx delay
When the driver was originally introduced in commit "6027384a phylib:
Add Atheros AR8035 GETH PHY support", the Tx delay was being
unconditionally enabled.
Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID
and RGMII_RXID", the author did not notice that code for enabling Tx
delay code was already. Therefore, the if condition for Tx delay has
always been useless for this PHY since this commit introduced it.
Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled.
After this patch, only those who define the interface as RGMII_TXID or
RGMII_ID will. This is to be expected, but will nonetheless break the
setups of those who didn't know they rely on Tx delay implicitly.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
menu: add support for client defined statusline function
Currently displaying status line is done in a weak function
menu_display_statusline().
bootmenu.c overrides the weak default function.
It calls menu_default_choice() and interprets the data as
struct bootmenu_entry.
pxe boot also uses common menu code for pxe menus.
If there is a system that enables both bootmenu and pxe,
menu_display_statusline() defined in bootmenu.c will be called
and it will interpret struct pxe_label as struct bootmenu_entry.
This leads to data aborts and pxe menu corruptions.
This patch adds support for client defined statusline function
to resolve the above bug.
Heiko Stuebner [Sun, 3 May 2020 11:26:34 +0000 (13:26 +0200)]
rsa: fix alignment issue when getting public exponent
To fill the exponent field of the rsa_public_key struct, rsa_mod_exp_sw
did a cast to uint64_t of the key_prop->public_exponent field.
But that alignment is not guaranteed in all cases.
This came to light when in my spl-fit-signature the key-name exceeded
a certain length and with it the verification then started failing.
(naming it "integrity" worked fine, "integrity-uboot" failed)
key_prop.public_exponent itself is actually a void-pointer, fdt_getprop()
also just returns such a void-pointer and inside the devicetree the 64bit
exponent is represented as 2 32bit numbers, so assuming a 64bit alignment
can lead to false reads.
So just use the already existing rsa_convert_big_endian() to do the actual
conversion from the dt's big-endian to the needed uint64 value.
Fixes: fc2f4246b4b3 ("rsa: Split the rsa-verify to separate the modular exponentiation") Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
If dcache is switched OFF to ON state and if non-cached memory is
used, this non-cached memory must be re-declared as uncached to mmu
each time dcache is set ON.
Introduce noncached_set_region() to set this non-cached region's mmu
settings. Let architecture override it by defining it as a weak
function.
For ARM architecture, noncached_set_region() defines all noncached
region as non-cacheable.
Issue found on STM32MP1 platform using dwc_eth_qos ethernet driver,
when going from dcache OFF to dcache ON state, ethernet driver issued
TX timeout errors when performing dhcp or ping.
It can be reproduced with the following sequence:
dhcp
while true ; do
ping 192.168.1.300 ;
dcache off ;
ping 192.168.1.300 ;
dcache on ;
done
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Cc: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de>
Andre Przywara [Mon, 27 Apr 2020 18:18:03 +0000 (19:18 +0100)]
arm: juno: enable USB
The Juno board features a standard compliant EHCI/OHCI USB host
controller pair, which we can just enable.
The platform data is taken from the device tree.
This allows to use USB mass storage (the only storage on a Juno r0)
for loading.
At least on my board USB seems a bit flaky, I need two "usb reset"
sequences after the "usb start" to detect an USB hard drive.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Andre Przywara [Mon, 27 Apr 2020 18:18:01 +0000 (19:18 +0100)]
arm: juno: Enable OF_CONTROL
The Arm Juno board was still somewhat stuck in "hardcoded land", even
though there are stable DTs around, and one happens to actually be on
the memory mapped NOR flash.
Enable the configuration options to let the board use OF_CONTROL, and
add a routine to find the address of the DTB partition in NOR
flash, to use that for U-Boot's own purposes.
This can also passed on via $fdtcontroladdr to any kernel or EFI
application, removing the need to actually load a device tree.
Since the existing "afs" command and its flash routines require
flash_init() to be called before being usable, and this is done much
later in the boot process, we introduce a stripped-down partition finder
routine in vexpress64.c, to scan the NOR flash partitions for the
DT partition. This location is then used for U-Boot to find and probe
devices.
The name of the partition can be configured, if needed, but defaults
to "board.dtb", which is used by Linaro's firmware image provided.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Andre Przywara [Mon, 27 Apr 2020 18:17:59 +0000 (19:17 +0100)]
uart: pl011: Add proper DM clock support
Even though the PL011 UART driver claims to be DM compliant, it does not
really a good job with parsing DT nodes. U-Boot seems to adhere to a
non-standard binding, either requiring to have a "skip-init" property in
the node, or to have an extra "clock" property holding the base
*frequency* value for the baud rate generator.
DTs in the U-Boot tree seem to have been hacked to match this
requirement.
The official binding does not mention any of these properties, instead
recommends a standard "clocks" property to point to the baud base clock.
Some boards use simple "fixed-clock" providers, which U-Boot readily
supports, so let's add some simple DM clock code to the PL011 driver to
learn the rate of the first clock, as described by the official binding.
These clock nodes seem to be not ready very early in the boot process,
so provide a fallback value, by re-using the already existing
CONFIG_PL011_CLOCK variable.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[trini: Add <clock_legacy.h> for get_bus_freq() for layerscape
platforms] Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Andre Przywara [Mon, 27 Apr 2020 18:17:58 +0000 (19:17 +0100)]
arm: juno: Fix Juno address variables
The U-Boot documentation explains that variables ending with "_r" hold
addresses in DRAM, while those without that ending point to flash/ROM.
The default variables for the Juno board pointing to the kernel and DTB
load addresses were not complying with this scheme: they lack the
extension, but point to DRAM. This is particularly confusing since the
Juno board features parallel NOR flash, so there *is* a memory mapped
NOR address holding a DTB, for instance.
Fix the variables to use the proper names, changing initrd_addr to
ramdisk_addr_r on the way, which seems to be more prevelant and
documented. On the way adjust the FDT load address to be situated
*before* the kernel, since users happened to overwrite the DTB by the
kernel clearing its .BSS section during initialisation.
Also remove the fdt_high and initrd_high variables (which were set
to -1), to allow U-Boot moving those images around.
This should avoid many problems in the future, but breaks loading
Linux kernels < v4.2, since they expect the DTB to be loaded in the same
512MB region as the kernel. If you need to load such an old kernel,
please set fdt_high to either 0xffffffffffffffff or 0xa0000000 (if you
load the kernel to the beginning of DRAM).
That fixes loading debug kernels, which happened to overwrite the DTB on
certain setups.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Rasmus Villemoes [Tue, 18 Feb 2020 08:39:42 +0000 (08:39 +0000)]
include/eeprom.h: fix build errors
CMD_EEPROM and ENV_IS_IN_EEPROM can be selected independently, and
cmd/eeprom.o gets built in either case, so whether to declare the real
prototypes needs to follow the same logic as whether cmd/eeprom.c is
built. Otherwise a ENV_IS_IN_EEPROM=y, CMD_EEPROM=n build fails
cmd/eeprom.c:73:1: error: expected identifier or ‘(’ before ‘{’ token
{
While at it, fix the dummy replacements (at least assuming they are
meant to allow the code to compile) - they need to have the same type
as the expression they replace, or one gets errors such as
env/eeprom.c: In function ‘eeprom_bus_read’:
env/eeprom.c:37:8: error: void value not ignored as it ought to be
rcode = eeprom_read(dev_addr, offset, buffer, cnt);
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 6 May 2020 15:05:17 +0000 (11:05 -0400)]
Revert "mkimage: fit: Do not tail-pad fitImage with external data"
This has been reported to break booting of U-Boot from SPL on a number
of platforms due to a lack of alignment of the external data. The
issues this commit is addressing will need to be resolved another way.
Reported-by: Alex Kiernan <alex.kiernan@gmail.com> Reported-by: Michael Walle <michael@walle.cc> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Ley Foon Tan [Mon, 4 May 2020 10:41:55 +0000 (18:41 +0800)]
cache: l2x0: Fix missing write to Auxiliary Control Register
In commit f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override
bit") we removed writel to regs->pl310_aux_ctrl by accident. This
commit restores it back.
Fixes: f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
scripts/get_default_envs.sh: preserve order of multiple entries for same variable
It's possible that the default_environment[] array contains multiple
entries for the same variable, e.g. a setting from env_default.h based
on some CONFIG_* variable, and another from
CONFIG_EXTRA_ENV_SETTINGS. In such a case, the last setting takes
effect.
Hence, in order to be able to use the output from this script as an
CONFIG_DEFAULT_ENV_FILE and get the same default environment as one
currently has, we need to preserve the order. So only sort by the
variable name, and disable the last-resort comparison.
We could pipe the result through uniq to remove duplicate lines, but I
think there's some value in seeing that certain variables are defined
multiple times.
- Add DM model for P1010RDB
- Add I2C DM Model support for P1010RDB, T1042RDB, T2080, T4240RDB,
MPC8548CDS, T1024RDB, P4080, P3041DS, P2041RDB, P2020RDB, P1020RDB,
P5040DS
- Fix reference to READM.qe_firmware
Tom Rini [Mon, 4 May 2020 13:29:42 +0000 (09:29 -0400)]
Merge tag 'u-boot-imx-20200502' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
i.MX for 2020.07
----------------
- imxrt: fix LCD clock, fix doc
- new board: Coral Dev
- imx8: enable Cache in SPL. SNVS, update SCFW API
- imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading
- MX6ULL : is_imx6ull to include i.MX6ULZ
- Net: add config to enable TXC delay
Commit 69529c912059 ("net: pcnet: Switch to PCI memory access")
switched from PCI IO access to PCI memory access without updating
the I/O primitives. Contrary to SH, the primitives for memory
access and IO access are implemented differently. Thus doing
memory access with IO port primitives breaks the driver on
MIPS Malta board.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
projects / u-boot.git / log