configs: am62x: enable secure device configs by default
Enable the CONFIG_TI_SECURE_DEVICE by default
Non-HS devices will continue to boot due to runtime device type detection.
TI's security enforcing SoCs will authenticate each binary it loads by
comparing it's signature with keys etched into the SoC during the boot
up process. The am62x family of SoCs by default will have some level of
security enforcement checking. To keep things as simple as possible,
enable the CONFIG_TI_SECURE_DEVICE options by default so all levels of
secure SoCs will work out of the box
ESM MCU masks must be set to 0h so that PMIC can handle errors
that require attention for example SYS_SAFETY_ERRn. The required bits
must be cleared: ESM_MCU_RST_MASK, ESM_MCU_FAIL_MASK, ESM_MCU_PIN_MASK.
If PMIC expected to handle errors, make sure EVM is configured to
connect SOC_SAFETY_ERRz (Main) to the PMIC.
Note that even though the User Guide for TPS65941 for J721E mentions
that these bits are reset to 0h; it is not reflected once board boots to
kernel, possibly due to NVM configurations. Eithercase, it is best to
account for this from R5 SPL side as well.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
- Various typo fixes, pass -Werror to host tools builds, bdi cleanups,
fix hush and local variables, a FSL PCI fix and correct some python in
one of the tests.
Tom Rini [Thu, 4 May 2023 13:03:02 +0000 (09:03 -0400)]
Merge tag 'efi-2023-07-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2023-07-rc2
Documentation:
* treat documentation warnings as errors in CI
* adjust StarFive VisionFive 2 and SiFive Unmatched documentation
* man-page for cp
* correct description of uclass_get_device_by_of_path
* correct proftool usage
UEFI
* Fix documentation of EFI Python tests
* Rename efi_selftest Python test
We do not want to merge documentation that produces Sphinx warnings.
scripts/kernel-doc uses environment variable KDOC_WERROR to determine
if warnings should be treated as errors.
Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 19 Apr 2023 23:38:16 +0000 (11:38 +1200)]
efi: Rename the base efi self-test
This function uses the same base name as all the others in this file, so
it is not easy to run just that one test. Add a _base suffix so that it
can be run on its own.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The number of the partition that U-Boot SPL loads the main U-Boot from is
defined as 2 by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2. The
partition type GUID is not used currently.
Reword the description of the boot process to make it clearer.
Variable old_outdir cannot be used before assignment.
The assignment must occur before the try block.
tools/dtoc/test_fdt.py:796:26:
E0601: Using variable 'old_outdir' before assignment
(used-before-assignment)
Add missing space in assignment.
Fixes: a004f29464d1 ("binman: Tidy up _SetupDtb() to use its own temporary file") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Pali Rohár [Tue, 2 May 2023 17:53:57 +0000 (19:53 +0200)]
pci: fsl: Do not access PCI BAR0 register of PCIe Root Port
Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0.
PCIe Root Port does not have any PCIe memory, so returns zero when trying
to read from PCIe Root Port BAR0 and ignore any writes.
Marek Vasut [Sat, 22 Apr 2023 13:01:31 +0000 (15:01 +0200)]
cmd: bdinfo: Map fdt_blob and new_fdt to sysmem
Map fdt_blob and new_fdt to sysmem, otherwise $fdtcontroladdr
and bdinfo output do not match and the bdinfo output address
is not a valid address accessible via sandbox memory accessors.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Variable old_outdir cannot be used before assignment.
The assignment must occur before the try block.
tools/dtoc/test_fdt.py:796:26:
E0601: Using variable 'old_outdir' before assignment
(used-before-assignment)
Add missing space in assignment.
Fixes: a004f29464d1 ("binman: Tidy up _SetupDtb() to use its own temporary file") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
common: cli_hush: Restore clear local variable support
The u-boot hush shell doesn’t support the unset command to clear a
variable and therefore an empty value ("c=") should be a valid value
for the set_local_var function to clear the variable. This partial
reverts commit aa722529635c ("common: cli_hush: avoid dead code") and
only checks for a `=` in the string. Additionally explicit call the
unset_local_var function to remove the variable if the value is empty.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Simon Glass <sjg@chromium.org>
- Updates for starqltechn and other qualcomm platforms, hi3798mv200,
Broadcom Northstar, and mediatek platforms
- Drop omap5_uevm, and assorted TI platform updates
- Add MAX14526
Tom Rini [Tue, 4 Apr 2023 15:47:25 +0000 (11:47 -0400)]
arm: Remove omap5_uevm board
This platform is unsupported by TI and was never widely distributed. As
this is untested for a long while and missing some DM conversions,
remove it and related device tree files.
Errata doc: https://www.ti.com/lit/pdf/sprz457
Errata ID i2331 CPSW: Device lockup when reading CPSW registers
Details: A device lockup can occur during the second read of any CPSW
subsystem register after any MAIN domain power on reset (POR). A MAIN
domain POR occurs using the hardware MCU_PORz signal, or via software
using CTRLMMR_RST_CTRL.SW_MAIN_POR or CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR.
After these resets, the processor and internal bus structures may get
into a state which is only recoverable with full device reset using
MCU_PORz.
Due to this errata, Ethernet boot should not be used on this device.
Workaround(s): To avoid the lockup, a warm reset should be issued after
a MAIN domain POR and before any access to the CPSW registers. The warm
reset realigns internal clocks and prevents the lockup from happening.
Workaround above errata by calling do_reset() in case of cold boot in
order to trigger warm reset. This needs enabling SYSRESET driver in R5
SPL to enable TI SCI reset driver.
Daniel Golle [Wed, 12 Apr 2023 20:36:43 +0000 (21:36 +0100)]
pinctrl: mediatek: set R1/R0 in case pullen/pullsel succeeded
Commit dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and
related functions") changed the logic deciding to set R0 and R1
registers for V1 devices.
Before:
/* Also set PUPD/R0/R1 if the pin has them */
err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
if (err != -EINVAL) {
mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
}
Tracing mtk_pinconf_bias_set_pullen_pullsel shows that the function
always either returns 0 in case of success or -EINVAL in case any error
has occurred. Hence the logic responsible of the decision to program R0
and R1 has been inverted.
This leads to problems on BananaPi R2 (MT7623N) when booting from
SDMMC, it turns out accessing eMMC no longer works since
U-Boot 2022.07:
MT7623> mmc dev 0
Card did not respond to voltage select! : -110
The problem wasn't detected for a long time as both eMMC and SDMMC work
fine if they are used to boot from, and hence R0 and R1 were already
setup by the bootrom and/or preloader.
Fix the logic to restore the originally intended and correct behavior
and also change the descriptive comment accordingly.
Fixes: dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and related functions") Signed-off-by: Daniel Golle <daniel@makrotopia.org> Tested-By: Frank Wunderlich <frank-w@public-files.de>
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to 8.
The C7x and VPAC have been overwhelming the DSS's access to the DDR
(when it was accessing via the Non Real-Time (NRT) Queue), primarily
because their functional frequencies, and hence DDR accesses, were
significantly higher than that of DSS. This led the display to flicker
when certain edgeAI models were being run.
With the DSS traffic serviced from the RT queue, the flickering issue
has been found to be mitigated.
The am62a qos files are auto generated from the k3 resource partitioning
tool.
Section-3.1.12, "QoS Programming Guide", in the AM62A TRM[1], provides
more information about the QoS, and section-14.1, "System Interconnect
Registers", provides the register descriptions.
arm: mach-k3: j7200: Fix firewall warnings at boot time
J721E and J7200 have same file j721e_init.c which had the firewall
configs for J721E being applied on J7200 causing the warnings. Split the
firewalls for both the boards to remove those warnings.
board: Fix documentation for Snapdragon based Samsung and Qualcomm boards
The current documentation for Snapdragon based Samsung
and Qualcomm boards is vague in the sense that at one place
it mentions that u-boot can be used as a replacement for ABL
bootloader and at another it mentions that u-boot is loaded
as an Android boot image through ABL.
K3 devices have some firewalls set up by ROM that we usually remove so
that the development is easy in HS devices.
While removing the firewalls disabling a background region before
disabling the foreground regions keeps the firewall in a state where all
the transactions will be blacklisted until all the regions are disabled.
This causes a race for some other entity trying to access that memory
region before all the firewalls are disabled and causes an exception.
Since the background regions configured by ROM are in such a manner
that they allow all transactions, don't touch the background regions at
all.
arm: mach-k3: common: Default to non fitImage boot on HS-FS
Allow non fitImage bootflow on Field Securable (HS-FS) devices in
addition to GP, force fitImage boot only on Security enforced (HS-SE)
devices where signed images are necessary to maintain chain of trust.
On modern Qualcomm platforms including SDM845 a GENI SE QUP IP
description is supposed to be found in board device tree nodes,
the version of the IP is used by the GENI UART driver to properly
set an oversampling divider value, which impacts UART baudrate.
The change touches dragonboard845c and starqltechn board device
tree source files, a device tree node label to "debug" UART is
renamed to 'uart9' according to the naming found in Linux.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
serial: msm-geni: correct oversampling value based on QUP hardware revision
Starting from QUP v2.5 the value of oversampling is changed from 32
to 16, keeping the old value on newer platforms results on wrong set
UART IP clock divider, thus the asked baudrate does not correspond to
the actually set with all the consequencies for a user.
The change links the driver to a new Qualcomm GENI SE QUP driver
to get its hardware version and update the oversampling value.
Deliberately the code under CONFIG_DEBUG_UART_MSM_GENI is not touched,
since a wanted baudrate can be controlled by setting a modified
CONFIG_DEBUG_UART_CLOCK build time variable.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Konrad Dybcio [Fri, 21 Apr 2023 17:50:39 +0000 (20:50 +0300)]
serial: msm-geni: Use upstream Linux bindings
The name "se" is used in upstream Linux device trees and has been for
ages, long before this U-Boot-ism was introduced. Same goes for the
existing compatible. Get rid of that.
[vzapolskiy: removed a ready change in the driver] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
serial: msm-geni: fix a compile time warning from msm_serial_setbrg()
A compiler warns about a missing function prototype, which is valid
and fixed by converting the function into static one, also fix
interleaved local variable declarations and assignments.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Fixes: 324df15a292e ("serial: qcom: add support for GENI serial driver") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
serial: msm-geni: remove invalid se-clk clock name
There is only one clock supplier to the serial IP, thus getting it by
name is not needed, also note that "clock-names" property is not listed
under doc/device-tree-bindings/serial/msm-geni-serial.txt, and finally
"se-clk" clock name is invalid, if added, it shall get "se" value like
it's already described in Linux device tree documentation.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad Dybcio [Fri, 21 Apr 2023 17:50:35 +0000 (20:50 +0300)]
serial: msm-geni: Always bind before relocation
In preparation for supporting upstream Linux device trees on Qualcomm
platforms, make this the default behavior.
[vzapolskiy: extracted the driver change from a combination with dts changes] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
For whatever reason, likely a driver stub was copied from another
driver, the driver contains a bunch of unnecessary and confusing
includes like watchdog.h etc., the change reduces the list.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
This change adds a Qualcomm GENI SE QUP device driver as a wrapper for
actually enabled and used serial devices found on a board.
At the moment the driver is pretty simple, its intention is to populate
childred devices and provide I/O mem read interface to them as clients,
this is needed for GENI UART driver to set up a proper clock divider
and provide the actually asked baud rate.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
This adds a simple Northstar "BRCMNS" board to be used with
the BCM4708x and BCM5301x chips.
The main intention is to use this with the D-Link DIR-890L
and DIR-885L routers for loading the kernel into RAM from
NAND memory using the BCH-1 ECC and using the separately
submitted SEAMA load command, so we are currently not adding
support for things such as networking.
The DTS file is a multiplatform NorthStar board, designed to
be usable with several NorthStar designs by avoiding any
particulars not related to the operation of U-Boot.
If other board need other ECC for example, they need to
create a separate DTS file and augment the code, but I don't
know if any other users will turn up.
The original Northstar is an ARM SoC series that comprise
BCM4709x and BCM5301x and uses a dual-core Cortex A9, the
global timer and a few other things.
This series should not be confused with North Star Plus
(NSP) which is partly supported by U-Boot already.
The SoC is well supported by the Linux kernel and OpenWrt
as it is used in many routers.
Since we currently don't need any chip-specific quirks
and can get the system up from just the device tree, a
mach-* directory doesn't even need to be added, just
some small Kconfig fragments.
MAX14526 is a powerful extcon chip which allows detection of various
plugs like usb, mhl, uart, headset etc. This version of driver
implements support of AP-usb and CP-usb/uart paths.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # LG P880 T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
pci: auto: Remove PCI_CLASS_PROCESSOR_POWERPC autoconfig case
PCI autoconfig case for PCI_CLASS_PROCESSOR_POWERPC just prints debug
message and then calls autoconfig setup code like for any other standard
endpoint device. We do not need special debug message for it, so remove
this case and handle PCI_CLASS_PROCESSOR_POWERPC via default code path.
Currently, only the first MAC address is read from the fuses.
The second MAC address is not read and Linux assigns a random one.
To prevent this behavior, read the second MAC address from the fuses
and store it into the eth1addr environment variable so that it
can be passed to Linux.
Eduard Strehlau [Wed, 26 Apr 2023 16:04:56 +0000 (13:04 -0300)]
smegw01: Switch to fitImage
Instead of loading the zImage kernel and the devicetree separately, switch
to the fitImage format, which is more convenient when working with secure
boot, for example.
Signed-off-by: Eduard Strehlau <eduard@lionizers.com> Signed-off-by: Fabio Estevam <festevam@denx.de>
Eduard Strehlau [Wed, 26 Apr 2023 16:04:54 +0000 (13:04 -0300)]
smegw01: Enable EMMC boot from multiple partitions
GPT Partition labels are used for determining the right
root filesystem to boot from.
The U-Boot environment is configured to reside in the eMMC hardware
boot partition we are currently booted from.
This should enable a dual copy approach for upgrading the bootloader.
One can overwrite the inactive hardware partition with new bootloader
and environment and afterwards switch the eMMC boot partition for an
atomic bootloader switch.
Signed-off-by: Eduard Strehlau <eduard@lionizers.com> Signed-off-by: Fabio Estevam <festevam@denx.de>
Eduard Strehlau [Wed, 26 Apr 2023 16:04:51 +0000 (13:04 -0300)]
smegw01: Add altbootcmd
Add an altbootcmd script, which is convenient way to integrate with
swupdate and perform a roll back of the previous working version in the
case of update failure.
Signed-off-by: Eduard Strehlau <eduard@lionizers.com> Signed-off-by: Fabio Estevam <festevam@denx.de>
Eduard Strehlau [Wed, 26 Apr 2023 16:04:50 +0000 (13:04 -0300)]
smegw01: Select bootcount support
Add automatic boot counter that increases after every
reset. After a power-on reset, it will be initialized with 1,
and each reboot will increment the value by 1. By default it is
disabled if bootlimit isn't set.
Signed-off-by: Eduard Strehlau <eduard@lionizers.com> Signed-off-by: Fabio Estevam <festevam@denx.de>
Hugo Villeneuve [Tue, 25 Apr 2023 14:19:35 +0000 (10:19 -0400)]
arm: imx8m: remove unused and obsolete board_fix_fdt() in SOC context
It doesn't seem appropriate for arch/SOC to use a board-level
functionality (CONFIG_OF_BOARD_FIXUP), because this prevents boards
that need to do FDT fixup from using that feature.
Also, this code is completely dead and useless (from comments by
Rasmus Villemoes on the mailing list):
- No in-tree imx8m-based board seems to set CONFIG_OF_BOARD_FIXUP
- The nodes which that function wants to disable don't even exist in
the U-Boot copy of imx8mp.dtsi.
This code was introduced in commit 35bb60787b88. It seems to be some
random import of code from downstream NXP U-Boot, with a commit
message that makes no sense in upstream context.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
imx6: clock: improve calculations to get the PLL video rate
During some tests to check the pixel clock rate in the transition from
U-Boot to the Linux kernel, I noticed that with the same configuration
of the registers the debug messages reported different rates.
The same Linux kernel calculations are now used to get the PLL video
rate.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Avoid a buffer overflow if assigned-clock-rates has less than two elements.
Fixes: 98bcdf16356c ("imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Patrick Wildt [Sun, 5 Feb 2023 23:48:26 +0000 (00:48 +0100)]
board: mntre: imx8mq: Add MNT Reform 2 board support
The MNT Reform 2 is a modular DIY laptop. In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM. Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.
pci: mpc85xx: Do not access PCI BARs registers of BDF address 00:00.0
At BDF address 00:00.0 is fictional device which PCI configuration header
is for configuring mpc85xx PCI controller itself. PCI config space of this
device has ATMU inbound registers on position of PCI BARs. Trying to do PCI
auto configuration of this device cause rewriting ATMU inbound registers.
To avoid it, do not allow overwriting registers at BARs positions. And
because this device does not have any PCI memory, return zeros when trying
to read PCI BARs config space registers. It signals to auto configuration
tool to not allocate any PCI memory for this device.
This information is taken from MPC8544E Reference Manual, sections
17.3.1.3, 17.3.1.1.1, 17.3.2 and 17.3.2.11. Available at NXP website:
https://www.nxp.com/docs/en/reference-manual/MPC8544ERM.pdf
pci: mpc85xx: Do not try to access extended PCIe registers
Driver pci_mpc85xx.c is PCI controller driver for old PCI Local Bus,
which does not support access to extended PCIe registers (above 0xff),
as opposite of the PCIe driver pcie_fsl.c for the same platform.
So do not try to access extended PCIe registers as it cannot work.
pci: mpc85xx: Allow 8/16-bit access to PCI config space
This Freescale mpc85xx PCI controller should support 8-bit and 16-bit read
and write access to PCI config space as described in more Freescale
reference manuals.
This change fixes issue that 8-bit and 16-bit write to PCI config space
caused to clear adjacent bits of 32-bit PCI register.
Christophe Leroy [Fri, 27 Jan 2023 13:51:06 +0000 (14:51 +0100)]
mpc83xx: Don't allow W and G bits in IBATs
The "Programming Environments Manual for 32-Bit Implementations of the
PowerPC™ Architecture" says "W and G bits are not defined for IBAT
registers. Attempting to write to these bits causes boundedly-undefined
results"
The "e300 Power Architecture™ Core Family Reference Manual" says the
same: "Neither the W or G bits of the IBAT registers should be set.
Attempting to write to these bits causes boundedly-undefined results."
Remove the possibility to set those bytes.
Fixes: 30915ab95d9 ("mpc83xx: Migrate BATS config to Kconfig") Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Mario Six <mario.six@gdsys.cc>
projects / u-boot.git / log