Nikhil M Jain [Thu, 20 Apr 2023 12:11:08 +0000 (17:41 +0530)]
drivers: video: Enable necessary video functions at SPL
To support video driver at SPL use CONFIG_IS_ENABLED and CONFIG_VAL,
which checks for stage specific configs and thus enables video support
at respective stage.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Nikhil M Jain [Thu, 20 Apr 2023 12:11:07 +0000 (17:41 +0530)]
common: Makefile: Rule to compile bmp.c
Add rule to compile bmp.c at SPL and u-boot proper when CONFIG_SPL_BMP
and CONFIG_BMP are defined.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Nikhil M Jain [Thu, 20 Apr 2023 12:11:06 +0000 (17:41 +0530)]
cmd: bmp: Split bmp commands and functions
To enable splash screen at SPL, need to compile cmd/bmp.c which also
includes bmp commands, since SPL doesn't use commands split bmp.c into
common/bmp.c which includes all bmp functions and cmd/bmp.c which only
contains bmp commands.
Add function delclaration for bmp_info in video.h.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Nikhil M Jain [Thu, 20 Apr 2023 12:11:05 +0000 (17:41 +0530)]
common: Kconfig: Add BMP configs
Add CONFIG_BMP and CONFIG_SPL_BMP which enable displaying bmp images at
u-boot proper and SPL.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Nikhil M Jain [Thu, 20 Apr 2023 12:11:04 +0000 (17:41 +0530)]
common: Makefile: Add rule to compile splash and splash_source at SPL
To enable splash screen and loading bmp from boot media, add rules to
compile splash.c and splash_source.c at SPL stage only when
CONFIG_SPL_SPLASH_SCREEN and CONFIG_SPL_SPLASH_SOURCE are defined.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Nikhil M Jain [Thu, 20 Apr 2023 12:11:03 +0000 (17:41 +0530)]
drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPL
To enable TIDSS driver only at SPL stage add rule to compile the TIDSS
video driver.
CONFIG_$(SPL_)VIDEO_TIDSS will compile tidss_drv, at SPL only if
CONFIG_SPL_VIDEO_TIDSS is defined and at u-boot proper if
CONFIG_VIDEO_TIDSS is defined.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Nikhil M Jain [Thu, 20 Apr 2023 12:11:02 +0000 (17:41 +0530)]
drivers: video: Makefile: Rule to compile necessary video driver files
To enable video driver at SPL, need to compile video-uclass,
vidconsole-uclass, backlight-uclass, panel-uclass, simple-panel, add
rules to compile them at SPL and u-boot proper. To support
splash_display at SPL, need to compile video-bmp, add rule to compile at
SPL and u-boot proper.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Nikhil M Jain [Thu, 20 Apr 2023 12:11:01 +0000 (17:41 +0530)]
drivers: Makefile: Add rule to compile video driver
Compile video driver at SPL using CONFIG_SPL_VIDEO.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
Nikhil M Jain [Thu, 20 Apr 2023 12:11:00 +0000 (17:41 +0530)]
drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL
To enable tidss display driver only at SPL stage, add necessary config,
CONFIG_SPL_VIDEO_TIDSS.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Nikhil M Jain [Thu, 20 Apr 2023 12:10:59 +0000 (17:40 +0530)]
drivers: video: Kconfig: Add configs for enabling video at SPL
Add Kconfigs which enable the video driver and splash screen at SPL
stage only and not at u-boot proper. The existing Kconfigs from u-boot
proper were not used to make SPL splash screen independent to them.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 23 Apr 2023 18:16:00 +0000 (06:16 +1200)]
patman: Declare the future Series memory
This member is used in series.MakeCcFile() so should be declared in the
Series class.
Add a declaration to silence the warning.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sun, 23 Apr 2023 16:15:56 +0000 (12:15 -0400)]
Merge tag 'u-boot-rockchip-
20230421' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add rk3588 evb support;
- Update pinctrl for rk3568 and rk3588;
- Update rk3288 dts;
- Update mmc support for rk3568 and rk3588;
- Add rng support for rk3588;
- Add DSI support for rk3568;
- Some other misc fixes in dts, config, driver;
Tom Rini [Sat, 22 Apr 2023 22:32:08 +0000 (18:32 -0400)]
Merge tag 'efi-2023-07-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2023-07-rc1-2
Documentation:
* Describe Python coding style
UEFI:
* Enable tests for authenticated capsules on the sandbox
* Fix pylint warnings
* Correct struct efi_hii_keyboard_layout definition
Tom Rini [Sat, 22 Apr 2023 22:31:46 +0000 (18:31 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
* Add StarFive VisionFive v2 Board support
* Support CONFIG_REMAKE_ELF
* Code cleanups for RISC-V architecture
Tom Rini [Sat, 22 Apr 2023 22:31:21 +0000 (18:31 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog
- watchdog: arm_smc_wdt: add watchdog support (Lionel)
- watchdog: ftwdt010: return a previously deleted driver now ported to
DM (Sergei)
- watchdog: Add a watchdog driver for Raspberry Pi boards (Etienne)
Tom Rini [Sat, 22 Apr 2023 22:30:56 +0000 (18:30 -0400)]
Merge tag 'u-boot-stm32-
20230419' of https://source.denx.de/u-boot/custodians/u-boot-stm
configs:
_ Add usb_pgood_delay for ST boards
_ increase malloc size for pre-reloc for stm32mp15
_ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15
dts:
_ Add QSPI support on STM32MP13x SoC family
_ Add FMC support on STM32MP13x SoC family
drivers/machine:
_ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()
_ spi: stm32_qspi: Remove useless struct stm32_qspi_flash
_ rawnand: stm32_fmc2: remove unsupported EDO mode
_ stm32mp: fix various array bounds checks
Tom Rini [Sat, 22 Apr 2023 22:30:31 +0000 (18:30 -0400)]
Merge tag 'u-boot-nand-
20230422' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
Pull request for u-boot-nand-
20230422
Replaces a patch by Linus Walleij merged with pull request
u-boot-nand-
20230417, with a newer version that contains fixes for tests
run by Tom Rini.
Linus Walleij [Fri, 7 Apr 2023 13:40:05 +0000 (15:40 +0200)]
mtd: rawnand: nand_base: Handle algorithm selection
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
D-Link DIR-885L and DIR-890L routers, we need to explicitly
select the ECC like this in the device tree:
nand-ecc-algo = "bch";
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
This is handled by the Linux kernel but U-Boot core does
not respect this. Fix it up by parsing the algorithm and
preserve the behaviour using this property to select
software BCH as far as possible.
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm]
Link: https://lore.kernel.org/all/20230407134008.1939717-3-linus.walleij@linaro.org/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Dario Binacchi [Sat, 22 Apr 2023 20:58:10 +0000 (22:58 +0200)]
Revert "mtd: rawnand: nand_base: Handle algorithm selection"
It will be replaced by a more recent version which contains fixes for
tests run by Tom Rini.
This reverts commit
ff33d3c87c2a1ab576607c2f67a9cb7690a4e7ca.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
FUKAUMI Naoki [Thu, 20 Apr 2023 12:00:41 +0000 (12:00 +0000)]
configs: rockchip: radxa-cm3-io: drop CONFIG_USB_DWC3_GENERIC
it's not used by rk35xx
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
FUKAUMI Naoki [Thu, 20 Apr 2023 12:00:40 +0000 (12:00 +0000)]
arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb
enable regulators for usb host function
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Thu, 20 Apr 2023 12:00:39 +0000 (12:00 +0000)]
configs: rockchip: radxa-cm3-io, rock-3a: enable commands for i2c/pmic/regulator
enable commands for i2c/pmic/regulator and relevant configs.
also drop configs for unused regulators.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
FUKAUMI Naoki [Thu, 20 Apr 2023 12:00:38 +0000 (12:00 +0000)]
configs: rockchip: rock-3a: make usb host work
add support for USB host function on ROCK 3A
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:45 +0000 (16:46 +0000)]
mmc: rockchip_sdhci: Limit number of blocks read in a single command
Using DMA to load TF-A into SRAM fails when booting from eMMC on RK3588.
## Checking hash(es) for Image atf-3 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-3' image node
spl_load_simple_fit: can't load image loadables index 2 (ret = -1)
mmc_load_image_raw_sector: mmc block read error
Fix this by using PIO mode in SPL and limit the number of blocks used in
a single read command to avoid triggering Data End Bit Error interrupt.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Geis [Tue, 18 Apr 2023 16:46:44 +0000 (16:46 +0000)]
mmc: sdhci: Allow disabling of SDMA in SPL
Rockchip emmc devices have a similar issue to Rockchip dwmmc devices,
where performing DMA to SRAM later causes issues with suspend/resume.
Allow us to toggle SDMA in SPL for sdhci similar to ADMA support, so we
can ensure DMA is not used when loading the SRAM code.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[jonas@kwiboo.se: add Kconfig default value and fix ADMA typo]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Jonas Karlman [Tue, 18 Apr 2023 16:46:42 +0000 (16:46 +0000)]
clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support
The device tree sdhci node reference the TMCLK_EMMC clock, add limited
support this clock to rk3588 cru driver. Fixes probe of sdhci driver.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:41 +0000 (16:46 +0000)]
rockchip: rk3588-rock-5b: Include eMMC node in SPL dtb
Add sdhci node to SPL and u-boot,spl-boot-order. Also add more supported
mmc modes and pinctrl.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:39 +0000 (16:46 +0000)]
mmc: rockchip_sdhci: Add support for RK3588
Add support for RK3588 to the rockchip sdhci driver.
Use driver data to handle differences between RK3568 and RK3588:
- Set "Receive original clock source is auto gating" for RK3588.
- Set "Receive clock source is no-inverted" only on RK3568 and "Transmit
clock source is invertion of original clock input" for RK3588.
- Use different txclk_tapnum for HS400 modes on RK3588.
- Configure the CMDOUT reg for HS400 modes for RK3588.
This is based on the mainline linux and vendor kernel driver and have
successfully been tested with rock5b-rk3588_defconfig and
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_SPEED_MODE_SET=y
using the following command to switch mode and then read 512 MiB of data
from eMMC into memory,
=> mmc dev 0 0 <mode> && mmc info && mmc read
10000000 2000 10000
for each of the modes below.
0 = MMC legacy
1 = MMC High Speed (26MHz)
3 = MMC High Speed (52MHz)
4 = MMC DDR52 (52MHz)
10 = HS200 (200MHz)
11 = HS400 (200MHz)
12 = HS400ES (200MHz)
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:38 +0000 (16:46 +0000)]
rockchip: rk3568-rock-3a: Enable support for more eMMC modes
Add supported mmc modes to rk3568-rock-3a device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:37 +0000 (16:46 +0000)]
mmc: rockchip_sdhci: Fix HS400 and HS400ES mode on RK3568
Adjust tap number for transmit clock, tap number and delay number for
strobe input to fix HS400 modes on RK3568.
New values have been picked from vendor kernel and u-boot and have
successfully been tested with rock-3a-rk3568_defconfig and
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_SPEED_MODE_SET=y
using the following command to switch mode and then read 512 MiB of data
from eMMC into memory,
=> mmc dev 0 0 <mode> && mmc info && mmc read
10000000 2000 10000
for each of the modes below.
0 = MMC legacy
1 = MMC High Speed (26MHz)
3 = MMC High Speed (52MHz)
4 = MMC DDR52 (52MHz)
10 = HS200 (200MHz)
11 = HS400 (200MHz)
12 = HS400ES (200MHz)
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:35 +0000 (16:46 +0000)]
mmc: rockchip_sdhci: Rearrange and simplify used regs and flags
This rearrange and remove duplicate defines to make the code cleaner.
There is no need to read vendor area1 and use an offset each time, it is
easier and clearer to just use the reg offset defined in TRM, same as
the other vendor regs.
This also removes use of the misspelled const for the RK3588 CMDOUT reg,
it will be re-added when support for RK3588 is introduced.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:34 +0000 (16:46 +0000)]
mmc: rockchip_sdhci: Remove empty get_phy and set_enhanced_strobe ops
Remove empty implementations of get_phy and set_enhanced_strobe ops.
Change driver set_enhanced_strobe to return 0 in order to allow missing
implementation of the ops.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:33 +0000 (16:46 +0000)]
mmc: rockchip_sdhci: Update speed mode controls in set_ios_post
Refactor set_ios_post ops to correctly set UHS Speed Select field values
according to TRM. Also set or unset Enhanced Strobe Enable bit and
eMMC Card present bit in set_ios_post, the Enhanced Strobe Enable bit
was never unset after switching to HS400ES mode.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:31 +0000 (16:46 +0000)]
mmc: rockchip_sdhci: Refactor execute tuning error handling
Check return value from mmc_send_cmd and clear HOST_CONTROL2 when there
is an error. Also skip enable of interrupt signaling and remove a delay,
a delay is already happening in sdhci_send_command.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Thu, 20 Apr 2023 15:55:15 +0000 (15:55 +0000)]
mmc: rockchip_sdhci: Use set_clock and config_dll sdhci_ops
Change to configure clock and DLL in set_clock and config_dll ops
instead of in the set_ios_post ops.
With this change the output clock is turned off while configuring DLL
parameters, according to the design recommendations.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:29 +0000 (16:46 +0000)]
mmc: rockchip_sdhci: Add set_clock and config_dll sdhci_ops
Add support for the set_clock and config_dll sdhci_ops. Use of these ops
will allow configuration of DLL while the output clock is disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:27 +0000 (16:46 +0000)]
mmc: rockchip_sdhci: Remove unneeded emmc_phy_init
Remove the unneeded emmc_phy_init now that the no-inverter flag is
handled correctly after commit
2321a991bbb5 ("rockchip: sdhci: rk3568:
bypass DLL when clk <= 52 MHz").
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:26 +0000 (16:46 +0000)]
mmc: rockchip_sdhci: Fix use of device private data
The device private data is misused in rockchip_sdhci_of_to_plat and
rockchip_sdhci_execute_tuning.
In these functions dev_get_priv is assigned to struct sdhci_host:
struct sdhci_host *host = dev_get_priv(dev);
Instead, the sdhci host should refer to host in struct rockchip_sdhc:
struct rockchip_sdhc *priv = dev_get_priv(dev);
struct sdhci_host *host = &priv->host;
Because host is the first member in struct rockchip_sdhc this is not a
real problem, lets fix it anyway and also use priv name consistently.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:24 +0000 (16:46 +0000)]
mmc: sdhci: Set UHS Mode Select field for UHS SDR25 mode
Set correct UHS Mode Select field value for UHS SDR25 (50MHz) mode.
Fixes: d1c0a2200afb ("mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 18 Apr 2023 16:46:23 +0000 (16:46 +0000)]
mmc: sdhci: Fix HISPD bit handling for MMC HS 52MHz mode
Set High Speed Enable bit for MMC High Speed (52MHz) mode.
Fixes: f12341a95295 ("mmc: sdhci: Fix HISPD bit handling")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Thu, 13 Apr 2023 14:13:03 +0000 (09:13 -0500)]
ARM: dts: rockchip: rk3588s-u-boot: Add rng node
Add a node for the trng found on RK3588 SoCs.
Changes in V3:
- Added Reviewed-By tag.
Changes in V2:
- None
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Chris Morgan [Thu, 13 Apr 2023 14:13:02 +0000 (09:13 -0500)]
rockchip: rng: add trngv1 for rk3588
This adds support for the TRNG found in the RK3588 SoC to the
rockchip_rng driver so that it can be used for things such as
seeding randomness to Linux.
Changes in V3:
- Moved notes from commit to cover letter.
- Added Reviewed-By tag.
Changes in V2:
- Modified Kconfig to note that the Rockchip RNG driver supports all
versions of the hardware (v1, v2, and the trng in the rk3588).
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 17 Apr 2023 19:07:25 +0000 (19:07 +0000)]
clk: rockchip: rk3568: Add dummy I2S1_MCLKOUT_TX clock support
A RK3568 device tree pmic node can reference the I2S1_MCLKOUT_TX clock
in assigned-clocks, add dummy support to set parent of this clock to the
rk3568 cru driver.
Fixes probe of pmic driver and missing regulators on affected boards,
rk3568-evb and rk3568-rock-3a.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 17 Apr 2023 19:07:23 +0000 (19:07 +0000)]
pinctrl: rockchip: Fix IO mux selection on RK3568
IO mux selection is not working correctly for all pins. Sync mux route
data from linux to add any missing and update wrong trigger pins to fix
this. Also apply the pull-up fix needed for GPIO0 D3-D6.
Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Jonas Karlman [Mon, 17 Apr 2023 19:07:21 +0000 (19:07 +0000)]
rockchip: rk3588: Sync sdmmc node from linux-next
Sync the sdmmc node from linux-next, include required nodes in SPL and
imply Kconfig options required for functional sdmmc clk in SPL and
U-Boot proper.
This make it possible for both SPL and U-Boot proper to configure sdmmc
clocks. In SPL, before TF-A is loaded, scru regs is configured, in
U-Boot proper a SCMI message is sent to TF-A.
Fixes: 95c8656b72dc ("ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 17 Apr 2023 19:07:20 +0000 (19:07 +0000)]
rockchip: rk3588: Add support for sdmmc clocks in SPL
Booting from sdmmc on RK3588 currently works because of a workaround in
the device tree, clocks are reordered so that the driver use ciu-sample
instead of ciu, and the BootRom initializes sdmmc clocks before SPL is
loaded into DRAM.
The sdmmc clocks are normally controlled by TF-A using SCMI. However,
there is a need to control these clocks in SPL, before TF-A has started.
This adds a rk3588_scru driver to control the sdmmc clocks in SPL before
TF-A has started, using scru regs. It also adds a small glue driver to
bind the scmi clock node to the rk3588_scru driver in SPL.
Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 17 Apr 2023 19:07:18 +0000 (19:07 +0000)]
clk: scmi: Add Kconfig option for SPL
Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options
enabled and SPL_FIRMWARE disabled result in the following error.
drivers/clk/clk_scmi.o: in function `scmi_clk_gate':
drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate':
drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate':
drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_probe':
drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel'
make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
make: *** [Makefile:2043: spl/u-boot-spl] Error 2
Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 17 Apr 2023 19:07:17 +0000 (19:07 +0000)]
rockchip: rk35xx: Enable fdtoverlay and kernel compression
Add fdtoverlay_addr_r, kernel_comp_addr_r and imply use of
OF_LIBFDT_OVERLAY on RK3568 and RK3588 to support fdtoverlay
and kernel compression.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jonas Karlman [Mon, 17 Apr 2023 19:07:15 +0000 (19:07 +0000)]
rockchip: rk35xx: Fix boot with a large fdt blob
The TF-A blobs used to boot RK3568 and RK3588 boards is based on atf
v2.3. Mainline atf v2.3 contains an issue that could lead to a crash
when it fails to parse the fdt blob being passed as the platform param.
An issue that was fixed in atf v2.4.
The vendor TF-A seem to suffer from a similar issue, and this prevents
booting when fdt blob is large enough to trigger this condition.
Fix this by implying SPL_ATF_NO_PLATFORM_PARAM to let u-boot pass a
NULL pointer instead of the fdt blob as the platform param.
This fixes booting Radxa ROCK 3A after recent sync of device tree.
Fixes: 073d911ae64a ("rockchip: rk3568-rock-3a: Sync device tree from linux")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Jonas Karlman [Mon, 17 Apr 2023 19:07:14 +0000 (19:07 +0000)]
rockchip: rk3588-rock-5b: Fix sdmmc boot
Running U-Boot from a SD-card on ROCK 5 Model B fails to load atf using
DMA and prints debug_uart messages.
<debug_uart>
<debug_uart>
U-Boot SPL 2023.04-rc3 (Mar 12 2023 - 00:30:16 +0000)
Trying to boot from MMC1
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-1' image node
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Use fifo-mode to disable DMA in SPL, add same-as-spl to boot-order and
remove DEBUG_UART_ANNOUNCE option to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
John Keeping [Mon, 27 Mar 2023 11:01:10 +0000 (12:01 +0100)]
rockchip: otp: fix misc_read() return values
The documentation for misc_read() says:
Return: number of bytes read if OK (may be 0 if EOF), -ve on error
The Rockchip efuse driver implements this so it should return the number
of bytes read rather than zero on success. Fix this so that the driver
follows the usual contract for read operations.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
John Keeping [Mon, 27 Mar 2023 11:01:09 +0000 (12:01 +0100)]
rockchip: efuse: fix misc_read() return values
The documentation for misc_read() says:
Return: number of bytes read if OK (may be 0 if EOF), -ve on error
The Rockchip efuse driver implements this so it should return the number
of bytes read rather than zero on success. Fix this so that the driver
follows the usual contract for read operations.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
John Keeping [Mon, 27 Mar 2023 11:01:08 +0000 (12:01 +0100)]
rockchip: misc: fix misc_read() return check
misc_read() is documented to return the number of bytes read or a
negative error value. The Rockchip drivers currently do not implement
this correctly and instead return zero on success or a negative error
value.
In preparation for fixing the drivers, fix the condition here to only
error on negative values.
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Fri, 24 Mar 2023 18:53:07 +0000 (13:53 -0500)]
rockchip: video: Add support for RK3568 DSI Host
Add support for DSI Host controller on Rockchip RK3568. This driver
is heavily based on the Rockchip dw_mipi_dsi_rockchip.c driver in
Linux and the stm32_dsi.c driver in U-Boot. It should be easy to add
support for other SoCs as the only missing component from the mainline
driver is setting the VOP big or VOP little (which the rk3568 does
not have).
Driver was tested for use in sending commands to a DSI panel in order
to obtain the panel ID.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Fri, 24 Mar 2023 18:53:06 +0000 (13:53 -0500)]
drivers: phy: add Innosilicon DSI-DPHY driver
Add support for the Innosilicon DSI-DPHY driver for Rockchip SOCs.
The driver was ported from Linux and tested on a Rockchip RK3566
based device to query the panel ID via a DSI command.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonathan Liu [Thu, 23 Mar 2023 10:35:58 +0000 (21:35 +1100)]
ram: rk3399: add missing high row detection
For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin
prints:
"Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB"
U-Boot TPL prints:
"BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB"
Add missing high row detection so that U-Boot TPL prints Row=16, same as
the Rockchip ddr init bin:
"BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB"
Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 19 Mar 2023 18:39:51 +0000 (18:39 +0000)]
gpio: rockchip: Add support for RK3568 and RK3588 banks
The GPIO V2 controller on RK3568 and RK3588 works very similar to
prior generation, main difference is the use of a write mask in the
upper 16 bits and register address offset have changed.
GPIO_VER_ID is a new register at 0x0078 that is used to determine when
the driver should use new or old register offsets and values. Earlier
generation return 0x0 from this offset.
Refactor code and add support for the GPIO V2 controller used in RK3568
and RK3588.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Sun, 19 Mar 2023 15:06:23 +0000 (16:06 +0100)]
rockchip: configs: mk808: enable usb support
Enable usb support in the mk808_defconfig.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Sun, 19 Mar 2023 15:06:11 +0000 (16:06 +0100)]
rockchip: configs: mk808: change CONFIG_TPL_TEXT_BASE
Currently the Rockchip rk3066a u-boot-tpl.bin file needs
to add the characters "RK30", while the other SoCs replace
the first 4 bytes. Bring this in line with the rest by
lowering CONFIG_TPL_TEXT_BASE and update rockchip.rst
instructions.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Sun, 19 Mar 2023 15:05:57 +0000 (16:05 +0100)]
arm: dts: rockchip: sync rk3066/rk3188 DT files from linux-next v6.2-rc4
Sync rk3066/rk3188 DT files from Linux.
This is the state as of linux-next v6.2-rc4.
New nfc node for MK808 rk3066a.
CRU nodes now have a clock property.
To prefend dtoc errors a fixed clock must also be
included for tpl/spl in the rk3xxx-u-boot.dtsi file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Sun, 19 Mar 2023 15:05:43 +0000 (16:05 +0100)]
arm: dts: rockchip: rk3188-u-boot: add gpio-ranges
The gpio node names are made generic, but without
gpio bank ID. Add gpio-ranges to rk3188-u-boot.dtsi
for now till a better method is found.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Sun, 19 Mar 2023 15:05:27 +0000 (16:05 +0100)]
arm: dts: rockchip: rk3066a-u-boot: add gpio-ranges
The gpio node names are made generic, but without
gpio bank ID. Add gpio-ranges to rk3066a-u-boot.dtsi
for now till a better method is found.
Disable gpio6 as the driver gives an error code
on return as status.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Sun, 19 Mar 2023 15:02:18 +0000 (16:02 +0100)]
rockchip: gpio: rk_gpio: use ROCKCHIP_GPIOS_PER_BANK as divider
The current divider to calculate the bank ID can change.
Given the Rockchip TRM not all gpio-banks have 32 pins per bank.
The "gpio-ranges" syntax allows multiple items with variable number
of pins. Use a constant ROCKCHIP_GPIOS_PER_BANK as fixed divider.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Wed, 15 Mar 2023 18:34:24 +0000 (19:34 +0100)]
arm: dts: rockchip: rk3288: partial sync pwm nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the pwm nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Wed, 15 Mar 2023 18:34:13 +0000 (19:34 +0100)]
clk: rockchip: clk_rk3288: add PCLK_RKPWM
The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM
instead of PCLK_PWM. They have the same pclk_cpu parent,
so add PCLK_RKPWM to rk3288_clk_get_rate().
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Wed, 15 Mar 2023 18:34:01 +0000 (19:34 +0100)]
arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the vop/lvds/mipi/hdmi nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Wed, 15 Mar 2023 18:33:50 +0000 (19:33 +0100)]
arm: dts: rockchip: rk3288: partial sync edp node
The rk3288 edp node has a phy node in Linux with a clock
property while current U-Boot driver expects this clock
on position index 1. Move U-Boot-specific DT clock properties
to rk3288-u-boot.dtsi and partially sync the edp node.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Wed, 15 Mar 2023 18:33:38 +0000 (19:33 +0100)]
video: rockchip: rk_vop: add rk3288-dp compare string
In the current rk3288.dtsi file the compatible string for
the DisplayPort(DP) node ends with "edp". The string in the
binding ends with "dp" which conflicts with "cdn-dp" as a
search term. Add "rk3288-dp" as compare string to select
vop_id.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Wed, 15 Mar 2023 18:33:25 +0000 (19:33 +0100)]
arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the grf and pmu nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Wed, 15 Mar 2023 18:31:57 +0000 (19:31 +0100)]
arm: dts: rockchip: rk3288: move io-domains nodes
In order to better compare the Linux rk3288.dtsi version
with the U-Boot version move the io-domains nodes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jianqun Xu [Wed, 15 Mar 2023 15:32:15 +0000 (17:32 +0200)]
pinctrl: rockchip: support rk3588 pinctrl
Add support for Rockchip rk3588 variant of pinctrl.
The driver is adapted from the Linux driver.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[eugen.hristev@collabora.com:
port to latest U-boot, bring more changes from Linux
use translated pull values table]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
John Keeping [Thu, 23 Feb 2023 19:28:51 +0000 (19:28 +0000)]
rockchip: rk3288: Use ft_system_setup instead of ft_board_setup
ft_board_setup() should be availble for use in board files but using it
in the rk3288 machine file blocks this functionality.
ft_system_setup() is the more appropriate function to use in a machine
definition.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 28 Feb 2023 21:38:25 +0000 (21:38 +0000)]
rockchip: Use an external TPL binary on RK3588
There is no support to initialize DRAM on RK3588 SoCs using U-Boot TPL
and instead an external TPL binary must be used to generate a bootable
u-boot-rockchip.bin image.
Enable ROCKCHIP_EXTERNAL_TPL by default for RK3588, add build steps for
RK3588 to documentation and clean up CONFIG_BINMAN_FDT options.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jagan Teki <jagan@edgeble.ai>
Kever Yang [Thu, 2 Mar 2023 07:12:57 +0000 (15:12 +0800)]
board: rockchip: Add rk3588 evb
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for
rockchip and also a reference board for board vendors.
Hardware:
SoC: RK3588
DRAM: LPDDR4X 8GB
Debug: UART2 via USB
PCIe: 3x4 *1
SATA *2
HDMI out *2
HDMI IN *1
USB2.0 Host *2
USB3.0 Host *1
Type C *1
MIPI DSI panel
dts Sync from Linux v6.2.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@edgeble.ai>
Quentin Schulz [Wed, 1 Mar 2023 17:31:15 +0000 (18:31 +0100)]
rockchip: ringneck-px30: enforce ENV_IS_NOWHERE with Kconfig select
Instead of letting the compiler error out if CONFIG_ENV_IS_NOWHERE is
not selected by the user, let's just enforce it when the user builds for
Ringneck PX30 so that no check needs to be performed by the compiler and
the configuration is always valid.
Suggested-by: Tom Rini <trini@konsulko.com>
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 1 Mar 2023 17:31:14 +0000 (18:31 +0100)]
rockchip: puma-rk3399: enforce ENV_IS_NOWHERE with Kconfig select
Instead of letting the compiler error out if CONFIG_ENV_IS_NOWHERE is
not selected by the user, let's just enforce it when the user builds for
Puma RK3399 so that no check needs to be performed by the compiler and
the configuration is always valid.
Suggested-by: Tom Rini <trini@konsulko.com>
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Vasily Khoruzhick [Tue, 7 Mar 2023 21:26:46 +0000 (13:26 -0800)]
rockchip: sdhci: rk3568: fix clock setting logic
mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.
Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.
Fix it by using MAX(mmc->tran_speed, mmc->clock)
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Ilias Apalodimas [Thu, 6 Apr 2023 19:37:06 +0000 (22:37 +0300)]
efi_loader: Fix flexible array member definitions
When a structure contains a flexible array member, it is not supposed to be
included in arrays or other structs.
Quoting the C spec [0]
"Such a structure (and any union containing, possibly recursively, a
member that is such a structure) shall not be a member of a structure
or an element of an array."
IOW efi_hii_keyboard_layout should not include
struct efi_key_descriptor descriptors[]; since we use it at the
declaration of struct efi_hii_keyboard_package.
[0] https://www.dii.uchile.cl/~daespino/files/Iso_C_1999_definition.pdf
chapter 6.7.2.1
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Thu, 20 Apr 2023 17:49:47 +0000 (19:49 +0200)]
test: fix launch_efi()
We cannot use old_dtb in the finally block if it has not been assigned
before the try block.
test/py/tests/test_efi_fit.py:458:30:
E0601: Using variable 'old_dtb' before assignment (used-before-assignment)
Fixes: 8391f955494e ("test/py: Create a test for launching UEFI binaries from FIT images")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Fri, 14 Apr 2023 08:39:18 +0000 (10:39 +0200)]
sandbox: enable CONFIG_EFI_CAPSULE_AUTHENTICATE
Without CONFIG_EFI_CAPSULE_AUTHENTICATE=y the following tests are skipped:
* test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
* test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Thu, 13 Apr 2023 16:13:32 +0000 (18:13 +0200)]
test: fix pylint warning for capsule tests
Fix pylint warnings like:
* Class inherits from object
* Missing module description
* Missing class description
* First line of comment blank
* Superfluous imports
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Tue, 11 Apr 2023 18:18:07 +0000 (20:18 +0200)]
efi_loader: remove unused efi_capsule_authenticate
Remove an unused implementation of efi_capsule_authenticate().
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Wed, 19 Apr 2023 06:45:34 +0000 (08:45 +0200)]
doc: codingstyle: Python coding style
Indicate that we follow PEP8 and PEP257.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Samuel Holland [Mon, 20 Feb 2023 06:02:39 +0000 (00:02 -0600)]
riscv: Support CONFIG_REMAKE_ELF
Add flags to tell objcopy what kind of ELF to create.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Bin Meng [Thu, 13 Apr 2023 06:20:08 +0000 (14:20 +0800)]
riscv: Update alignment for some sections in linker scripts
Some sections in the linker scripts are aligned to 4 bytes, which
may cause misaligned exception on some platforms, e.g.: clearing
the bss section on 64-bit hardware if __bss_start does not start
from a naturally 8 bytes aligned address.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Bin Meng [Thu, 13 Apr 2023 06:20:07 +0000 (14:20 +0800)]
riscv: spl: Remove relocation sections
U-Boot SPL is not relocable. Drop these relocation sections.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Bin Meng [Thu, 13 Apr 2023 06:20:06 +0000 (14:20 +0800)]
riscv: Avoid updating the link register
board_init_r does not return for U-Boot SPL hence there is no need
to update the link register when jumping to board_init_r.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Bin Meng [Thu, 13 Apr 2023 06:20:05 +0000 (14:20 +0800)]
riscv: Change to use positive offset to access relocation entries
The codes currently skip the very first relocation entry, and have
an inaccurate comment "skip first reserved entry" indicating that
the first entry is reserved, but later it references the elements
in the first relocation entry using a minus offset.
Change to use a positive offset so that there is no need to skip
the first relocation entry.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Bin Meng [Thu, 13 Apr 2023 06:20:04 +0000 (14:20 +0800)]
makefile: riscv: Drop useless argument of prelink-riscv
The argv[2] is never used in prelink-riscv. Drop it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Thu, 13 Apr 2023 06:20:03 +0000 (14:20 +0800)]
tools: prelink-riscv: Unmap the ELF image when done
The codes forget to call munmap() to unmap the ELF image that was
mapped by previous mmap().
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Thu, 13 Apr 2023 06:20:02 +0000 (14:20 +0800)]
tools: prelink-riscv: Cosmetic style fixes
Some coding convention fixes.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Thu, 13 Apr 2023 06:20:01 +0000 (14:20 +0800)]
riscv: Optimize loading relocation type
't5' already contains relocation type so don't bother reloading it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Thu, 13 Apr 2023 06:20:00 +0000 (14:20 +0800)]
riscv: Optimize source end address calculation in start.S
The __bss_start is the source end address hence load its address
directly into register 't2' for optimization.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Fri, 7 Apr 2023 05:44:59 +0000 (13:44 +0800)]
riscv: Enforce DWARF4 output
Since commit
409e4b547872 ("Makefile: Enforce DWARF4 output") the
whole U-Boot build switched to enforce DWARF4 output, but RISC-V
is still on its own setting. Let's switch to use U-Boot's setting.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Bin Meng [Mon, 3 Apr 2023 03:37:32 +0000 (11:37 +0800)]
riscv: Correct a comment in io.h
Replace NDS32 with RISC-V in the comments.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Yanhong Wang [Thu, 16 Mar 2023 02:53:32 +0000 (10:53 +0800)]
configs: starfive: add starfive_visionfive2_defconfig
This is the initial basic config for StarFive VisionFive v2 board. It
includes consol, Norflash, sdio, ddr etc.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Yanhong Wang [Wed, 29 Mar 2023 03:42:23 +0000 (11:42 +0800)]
riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree
Add initial device tree for StarFive VisionFive v2 board.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Yanhong Wang [Wed, 29 Mar 2023 03:42:22 +0000 (11:42 +0800)]
riscv: dts: jh7110: Add initial u-boot device tree
Add initial u-boot device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Yanhong Wang [Wed, 29 Mar 2023 03:42:21 +0000 (11:42 +0800)]
riscv: dts: jh7110: Add initial StarFive JH7110 device tree
Add initial device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Yanhong Wang [Wed, 29 Mar 2023 03:42:20 +0000 (11:42 +0800)]
board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig
Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>